SU1298831A1 - Pulse repetition frequency multiplier - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to increase speed. The device contains shaper 1 pulses. dhed delay delay 2, reversible counter 3, digital adder 4, memory register 5. DAC 6 and controlled rr. 7, Short pulses. From the output of the imaging device I are fed to the input of the register 5, to the input of the delay unit 2, where they are delayed during the census of information from the adder 4 to the register.5, and to the input of the preliminary records H of the counter 3. The binary code of the control signal from the outputs of register 5 is applied to the bit inputs of the DAC 6. At the output of the DAC 6, a control voltage is obtained, the level of which determines the frequency of the signal at the output of g. 1, zl-ta delay 2, adder 4 and registra 5, 2 silt with S /) dtjiwd Yu SO oo 00 co

Description

The invention relates to a measurement technique and can be used to measure the phase characteristics of signals.

The circuit of the invention is an increase in speed.

Figure 1 shows a functional diagram of a pulse frequency multiplier; FIG. 2 shows timing diagrams explaining the operation of multipliers.

The pulse frequency multiplier contains a pulse former 1, a delay element 2, a reversible counter 3, a digital adder 4, a memory register 5, a digital-to-analog converter 6, a controlled oscillator 7,

The multiplier works as follows,

The input signal of the imager 1 receives an input signal in the form of a periodic sequence of pulses (FIG. 2a) Short impulses (FIG. 26) are formed on the front of the input signal, the duration of which is shorter than the maximum frequency of the signal at the output of the controlled oscillator 7 (FIG. 2d). at the output of the controlled oscillator 7 linearly depends on the level of the control voltage obtained from the output of the digital-analog converter 6, to the bit inputs of which is fed the binary code of the control signal from the outputs of the register 5 The short pulses from the output of the imaging unit 1 are fed to the input of the register 5 and to the input of the element 2, where the time of the census of information from the digital adder 4 to the register 5 is delayed. The type of signal at the output of the element 2 is shown in figv.

The pulses from the output of element 2 are fed to the input of the preliminary recording of the reversible counter 3, the preset inputs of which are supplied with the binary code of the K number (K is the multiplication factor of the pulse frequency multiplier). If the ratio of the frequency of the signal at the output of the controlled oscillator 7 to the frequency of the input signal is K, then the input of the reverse count of the reversible counter 31 (by the time of the arrival of the next

the pulse to the recording of the register of the 5) will go to the pulses and 0 will be set to the first group of inputs of the digital adder. In this case, the binary code of the control signal at the output of the register 5 does not change. When the input signal frequency changes, the binary code of the number from the outputs of the reversible counter 3, corresponding to the number of under count pulses (in the forward binary code) or recalculation (in the additional binary code) to the magnitude of the multiplication factor K, goes to the first group of inputs of the digital adder 4 , which leads to a change in the binary code of the control signal at the output of the register 5 by the error value and to a proportional change in the frequency of the signal at the output of the controlled oscillator 7,

Formula of Invention

A pulse frequency multiplier containing a reversible counter, serially connected digital-to-analog converter and a controlled oscillator, the output of which is connected to the reverse count input of a reversible counter, characterized in that, in order to increase speed, serially connected digital sum, mater and memory register are entered , series-connected pulse shaper and delay element, the output of which is connected to the pre-recording input of a reversible counter, bit outputs Reversible counter dyes are connected to the corresponding inputs of the first group of inputs of a digital adder, the inputs of the second group of inputs of which are combined with the corresponding bit inputs of the D / A converter and connected to the corresponding bit outputs of the memory register, the recording input of which is connected to the output of the pulse shaper, the inputs of the reverse setting the counters are the inputs of the multiplication factor setting, and the pulse driver input is the signal input of the multiplier Stages following the pulses.

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Claims (1)

Claim A pulse repetition rate multiplier comprising a reversible counter, a digital-to-analog converter connected in series, and a controlled generator, the output of which is connected to a countdown input of a reversible counter, characterized in that, in order to increase speed, a series-connected digital adder and a memory register are introduced, series-connected pulses and a delay element, the output of which is connected to the input of the preliminary recording of the reversible counter, the discharge outputs the dividing counter is connected to the corresponding inputs of the first group of inputs of the digital adder, the inputs of the second group of inputs are combined with the corresponding bit inputs 45. of the digital-to-analog converter and connected to the corresponding bit outputs of the memory register, the recording input of which is connected to the output of the pulse shaper, the inputs of the pre-installation of the reversible counter are the inputs of the setting of the multiplication coefficient, and the input of the pulse shaper is the signal input of the frequency multiplier 55 pulse. 12988CH '_________________ π □ шшплллтшииъ FIG. g