SU1596445A1 - Digital multiplier of recurrence rate of periodic pulses - Google Patents

Abstract

The invention can be used in meters and converters of low frequency signals. The purpose of the invention is to increase accuracy by reducing the output frequency step of the grid — by introducing a digital-to-analog converter 6, a 12-clock generator, and a shaper of 13 codes and the organization of new functional connections. The device also contains a clock pulse generator 1, an And 2 element, a divider 3 with a variable division factor, a 5 code converter, a storage register 8, a control pulse driver 9, a short pulse driver 10, a pulse counter 11, and input and output buses 7 and 4. The circuit converter 5 codes. 1 hp f-ly, 2 ill.

Description

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The invention relates to a pulse technique and can be used in devices for measuring and converting low-frequency signals.

The purpose of the invention is to improve accuracy by reducing the grid step of the output frequency

FIG. 1 shows the electrical structural diagram of the device; in fig. 2 - an example of the implementation of the converter codes

The periodic frequency pulse frequency multiplier contains the first clock pulse generator 1, the output of which is connected to the first input of the AND 2 element, the output of which is connected to the clock input of the divider 3 with a variable division factor (DDC), the output of which is connected to the output bus 4, the information inputs are connected with the first code output of the converter 5 codes, the second code output of which is connected via a digital-to-analog converter 6 (DAC) to the input (control) of the first generator 1 of clock pulses. The input bus 7 is connected to the input of the record of the storage register 8, through the driver of the control pulses 9 to the second input of the element 2 and through the driver of the pulses 10 to the trigger input of the converter 5 of the codes and to the reset input of the pulse counter 11, the clock input of which is connected to the output the second generator 12 clock pulses and with the clock input of the converter 5 codes, the first, second, third and fourth information inputs of which are connected respectively with the first, second, third code outputs of the imaging unit 13 codes and the outputs of the register 8 storage, the information inputs of which are connected to the outputs of the counter 11 pulses.

The decoder 5 codes contains the first multiplier 14 codes, the start input of which is connected to the converter start input 5 codes, the first information inputs of which are connected to the input of the first multiplier 14 codes, the outputs of which are connected through the first memory register 15 to the first code output of the 5 code converter, and with the input of the first operand of the second multiplier 16 codes, the input of the second operand of which is connected to the second information inputs of the converter 5 codes, the outputs are connected to the input of the first operand of the divider 17 to Dov, the input of the second operand of which is connected to the input of the second operand of the first multiplier 14 and with the fourth information inputs of the 5 code converter, the third information inputs of which are connected to the input of the first operand of the code read 18, the input of the second operand of which is connected to the output of the 17 code divider, outputs - through the second storage register 19 - with the second code output of the converter 5 codes, the clock input of which is connected to the clock inputs of the second multiplier 16 codes, the divider 17 codes and the clock input p The first multiplier 14 codes, the control output of which is connected to the recording input of the first storage register 15 and through the first delay element 20 to the start input of the second multiplier 16 codes, the control code of which is connected to the start input of the code divider 17, the control output of which the second delay element 21 is connected to the recording input of the second storage register 19 „

The periodic frequency pulse frequency multiplier is as follows

In the initial state, at the output of the former 9, the low level, by which element 2 is closed at the first entrance.

On the bus 7 with the frequency Fg, a periodic sequence of pulses is received. At the back of the pulse at the output of the former 10, the counter 11 is zeroed and the converter 5 is started. The counter 11 is filled with the pulses coming to its counting input from the generator 12.

The shaper 3 is designed in such a way that with the arrival of the second and subsequent input pulses a high level appears at its output, as a result of which element And 2 opens at the first input and through it pulses from the output of the generator 1 arrive at the clock input of the HFMA 3 towards the arrival of the next input and fflyly on bus 7 in counter 11 there is a code N, the value of which is equal to the ratio of the periods of the input and the filling counter 11 of the frequencies F / F where F. is the pulse frequency at the output of the generator 12. On the leading edge of the input pulse, code N is rewritten from counter 11 into the register 8o. The code corresponding to the number N comes from the output of register 8 to the fourth information inputs of the converter 5o. The first, second and third information inputs of the converter 5 are received from the three outputs of the driver 8 codes, corresponding to the coefficients a K El. aj -g -,

Fo

S

de S is the steepness of the regulating characteristic of the generator 1, Fg is the value of the frequency at the output of the generator 1 at a zero input control voltage;

K is the multiplication factor; the number is K-real and is represented as a binary code with a fixed point separating the integer part of the number K from the fractional. The output frequency of the device is equal to

BS + FO

vb1x

where A is the code supplied to the input of the PDKD 3;

B is the code supplied to the input of the D / A converter 6, To calculate the values of A and B, the converter 5 implements the following algorithm. After the end of the process of measuring the period of the input frequency and writing the code to the register 6 from the output of the imaging unit 10, a transform start pulse arrives at the trigger input of the converter 5 and starts the multiplier 14 After the multiplication cycle is performed, the output of the multiplier 14 is the code of the number A, which, by the signal From the control output of the multiplier 14 is stored in register 15, the delayed signal (the delay is equal to the propagation time of the signal from the outputs of the multiplier 14 to the outputs of register 15) is fed to the start input of the multiplier 16. Multiply cycle 1

Claims (1)

1. A digital frequency multiplier for following periodic pulses, containing a frequency divider with a variable division factor, the output of which is connected to the output bus, the clock input to the output of the And element, the first input of which is connected to the output of the first clock generator, the second input to the generator output control of their pulses, the input of which is connected by the 2nd input of the record of the storage register and, through a pulse shaper, to the reset input of the pulse counter, whose codes are connected 5 with information inputs of the storage register, characterized in that, in order to improve accuracy by reducing the output frequency grid step, the first clock generator 0 pulses are controllable and digital-analog input is entered into the device. converter, code converter, second clock generator and driver of codes, first, 5, the second and third code outputs of which are connected respectively with the first, second and third information inputs of the code converter, the fourth information inputs of which 0 connected to the outputs of the register stored. Nor, the first code output - with information inputs of a frequency divider with a variable division factor, the second code output through a digital-to-analog converter - with the input of the first clock generator, the start input is connected to the reset input of the pulse counter, the count input 5 of the code aj 1 A comes from the outputs multiplier 16 at the input of the divider 17, which divides the numbers according to the signal received at the start input of the divider 17. At the end of the division cycle B, register 19 records the code for number B, where is A a number, N, which is obtained by truncating the fractional part thereof, thus the converter 5 has a function for calculating the parameters A and B necessary for controlling DPKD 3 and 6 through the DAC generator 1,