SU1620956A1 - Digital phase shifter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital information conversion systems with phase-pulse modulated signals. The goal is to improve the accuracy of phase shifts by reducing the discreteness of setting phase delays - achieved by adding an adder 6 modulo two and a reversible counter 7 to the digital phase shifter. The digital phase shifter also contains 1 pulse generator, 2 frequency divider, triggers 3. 5. 2 or .

Description

Schig.1

The invention relates to a pulse technique and can be used in digital information conversion systems with phase-pulse modulated signals.

The purpose of the invention is to improve the accuracy of phase shifts by reducing the discreteness of setting phase delays.

FIG. 1 shows a phase diagram of the phase shifter; in fig. 2 - time diagrams of his work.

The phase shifter contains a pulse generator 1, the output of which is connected to the input of frequency divider 2, the first trigger 3, the output of which is connected to the output bus 4 of the device, the second trigger 5, an adder 6 modulo two and a reversible counter 7, informational hours whose strokes are connected to the bus 8 sets the phase code, and the write enable input - with the clock input of the second trigger 5, l-K-inputs of the first trigger 3 and the output of the adder 6 modulo two, the first input of which is connected to the output of the frequency divider 2, the input of which is connected to the countdown input R Eversive counter 7, the loan output of which is connected to the clock input of the first trigger 3, the output of which is connected to the second input of the adder 6 modulo two, the third input of which is connected to the output of the second trigger 5, the D input of which is connected to the input 9 of the digit digit of the phase code .

Phaser works as follows.

From the output of the hgchetora 1, the clock frequency pulses (FIG. 2a) are sent to frequency divider 2 and reversing counter 7.

The phase code (Fig. 2c) and the phase sign (Fig. 2d) are received at the input of the phase shifter. Suppose that the first 3 and second 5 triggers are in the state O (the time interval from 0 to T1 in FIG. 2). The reversible counter 7 is in parallel recording mode, since at the output of the adder 6 modulo two (Fig. 2e) is state O. At time T1, at the output of divider 2 (Fig. 26) a transition occurs from the signal level 0-1 At this moment there is a recording in the second (Fig. 2g) trigger 5 of the phase sign and the transfer of the counter 7 to the countdown mode. When the state of the counter 7 passes through zero, a loan pulse is generated (T2 - TZ, Fig. 2e), which transfers the first trigger 3 to the opposite state (T2, Fig. 2e), which puts the device in the write mode of the phase code. As a result

the phase shift on the output bus 4 relative to the output of the divider 2 is determined by the formula

 C + 0.5) 1,

where N is the division factor of divider 2;

i - signed phase code;

 T - period of the clock frequency of the generator 1.

In the Phase modulator mode, the systematic error is 0.5 discrete

phase shift is not significant since

constant and in phase calibrator mode,

when the phase difference between the reference is important

the frequency from the output of divider 2 and output,

then one of these frequencies can be stung

through the trigger corresponding front

clock frequency.

FIG. 2 shows diagrams of the operation of the phase shifter for different values of the phase code. The interval T1 - TZ corresponds to a zero code value, T4 - T8

-positive code values, T9 - T10

-negative values of the phase code.

Compared with the known, the proposed technical solution makes it possible to reduce the sampling step by more than three times (with the known device, the sampling step is 18 °, and in the proposed 55 °).

Claims (1)

Formula of Invention A digital phase shifter comprising a pulse generator, the output of which is connected to the input of a frequency divider, the first trigger, the output of which is connected to the output bus of the phase shifter, and the second trigger, characterized in that, in order to improve the accuracy of setting phase shifts by reducing the discreteness of changing phase delays, it is entered by a modulo two adder and a reversible counter, the information inputs of which are connected to the phase code setting bus, and the write enable input - to the clock input of the second trigger, the J-K inputs of the first trigger and output modulo two, the first input of which is connected to the output of the frequency divider, the input of which is connected to the countdown input of the reversible counter, the output of the loan which is connected to clock input of the first trigger connected to the second input of the modulo two adder, the third input of which is connected to the output of the second trigger, the D input of which is connected to the input of the sign bit code phase, with the divider 4acTOf s made in the form of a binary counter. I y d About T1TPZ G4 PTB 77 FIG. 2 TV G9 BY