SU1413590A2 - Device for time scale correction - Google Patents

Abstract

The invention relates to a measurement technique and can be used in chronometric systems for the correction of secondary time scales. The aim of the invention is twisting-- correction speed with significant

Description

eooff correction

at

9-chi

go

differences in time scales. The device provides serial and parallel inputs for the correction of a secondary time scale containing a generator 1, a phase shifter unit 2, and a divider 3 frequencies. With a sequential input, the correction code passes through the correction code converter 6 and fills shift register 5. The input end signal is generated by a counter 8, a decoder 9 and a single pulse shaper 10. At this output of the driver 1 1 of the control signals, the resolving potential is established, after which the correction code is rewritten from the shift register 5 to the reversible counter 4 using the element AND 7. Phase shifting

block 2 changes its division factor by the time corresponding to the value of the correction information recorded in the reversing counter 4. After parallel input to the shift register 5 from memory 12, a constant correction code is quickly recorded equal to its full range. Recording is done with the help of the element OR 13, the driver of 14 pulses p of the inverter 15 and the second element of And 16. At the same time, if the time scales differ by more than 2 times the correction range, then a set of several fast parallel and one slow serial inputs correction rate. 5 il.

one

The invention relates to the field of measurement technology and can be. used in chronometric systems for the correction of secondary time scales.

The aim of the invention is to improve the speed of correction with significant discrepancies in time scales.

FIG. 1 shows a block diagram of the device; figure 2 is a functional diagram of the correction code converter; figure 3-5 - timing charts of the device.

The device contains a generator 1, a phase shifter 2, a frequency divider 3, a reversible counter 4, a shift register 5, a correction code converter 6, the first element I7, a counter 8, a decoder 9, a single pulse shaper 10, a shaper of control signals 1Л, a memory block 12 , the element OR 13, the pulse shaper 14, the inverter 15 and the second element AND 16. The converter of the correction code 6 contains the trigger 17, the element OR 18 and the delay element 19.

The inputs of the positive and negative correction devices are connected to two inputs of the element OR 13 and two identical inputs of the memory block 12, the parallel outputs of which are connected to the corresponding parallel

the inputs of the shift register 5 connected by the pre-recording input to the -: output of the pulse driver 14 and the input of the inverter 15. The output of the decoder 9 is connected to the input of the single pulse generator 10 via an AND 16 element, the second input of which is connected to the output of the inverter 15, and the transducer, OR 13 is connected to the input of the pulse shaper 14.

The driver of the control signal 11 is made on a QC trigger, wherein the input P of the trigger is the first input of the driver 11, the input C is the second

the input, the trigger output - the output of the forcer 11. On the input To fed Oh, to another input of the trigger 1.

The device works as follows.

Generator 1 is a pulse source (4 m) for starting phase shifting unit 2, which is implemented as a frequency divider with a variable division factor. In the initial state, the division factor is equal to K, which is determined by the presence of a phase O level 2 on the second control input (FIG. 4 l), regardless of the signal on the first control

the entrance. From the output of the phase-shifting unit 2, pulses are applied to frequency divider 3 (FIG. 4 n).

The device has two modes of operation: correction of the time scale by an amount determined by the correction code entered into the device; correction of the time scale by a fixed amount stored in memory 12 without inputting a correction code to the device.

In the first mode, the operation is carried out as follows.

The correction input is sent to the bus (Fig. 4a), which is fed to the input of the setting of the bits of the counter 7. In this case, the counter 8 is reset and the output of the decoder 9 is O (Fig. 4c). This signal is fed to the first input of the element AND 16, at the second input of which there is a level L from the output of the inverter 15. At the output of the element 16, a level O appears (Fig. 4a), which is fed to the first input of the imaging unit 10.

On the bus, the correction code is entered into the device by a n-bit serial and or binary binary correction code with high-order bits along two lines of communication in the form of a direct and inverse code. The lower-order code contains information about the correction sign . The correction code is fed to the converter 6.

The direct code pulses (Fig. 3a) are fed to the S input of the trigger 17 (Fig. .. correction code converter 6, and the inverse code pulses (Fig. 36) to the R input of the trigger 17. These same pulses are fed to the inputs of the element OR 18, at the output of which a clock train of pulses is formed (Fig. 3g). At the output of trigger 1-7, direct code pulses are formed (Fig. 3c), and their duration is increased to the period of repetition of clock pulses at the output of the OR element 18. From the output of the trigger 17, the pulses of the direct code are fed to the information output of the converter 6 and then to the information input of the shift register 5. The pulses of the clock series from the output of the element OR 18 are transmitted through the delay element 19 to the clock output of the converter 6 (FIG. 3 d) and then to the clock input of the shift register 5. At the same time

clock pulses relative to forward code pulses ensure reliable recording of information in the shift register 5.

d

15 20

5 ZO

about 45 CQ i

five

The direct correction code is written to shift register 5. At the same time, counter 8 counts the number of pulses of a clock train. As soon as all n bits of the code are recorded in the shift register 5, the output of the decoder 9 is Level 1 (Fig. 4c), which is fed to the first input of the And 16 element. At the output of And 16, the level 1 appears (Fig .4 h), which is fed to the first input of the shaping unit 10. The imaging unit 10 selects the second pulse after appearance (1 of figure 4) from the pulse train at the second input. This pulse (Fig. 4 and) is fed to the second input of shaper I to the input of the preliminary recording of the reversible counter 4, the code being rewritten from the higher n-1 bits of the shift register 5 to the reversing counter 4 on the front of the pulse. When writing to the reversible counter 4 a number other than O, level 1 appears at its output (FIG. 4k), which, arriving at the first input of shaper 11, allows the formation of a control signal at its output. The control signal in the form of a level I appears at the output of the shaper 11 through a cut of the pulse at the exit of the shaper 10 (FIG. 4 L).

The control signal is applied to the second control input of the phase-shifting unit 2 and changes its division factor by K + I depending on the sign coming from the low-order output of the shift register 5 (Fig. 4 and). At the same time, the control signal opens the element AND 7, the pulses from the output of the phase-shifting unit 2 begin to pass to the input of the subtraction of the reversible counter 4 (Fig. 4 o).

With the division factor K-1, the first after changing the division factor the pulse at the output of the photo-shifting unit 2 takes place at Tf-time earlier than with the initial division factor, the second one — 2T earlier, and so on. At the division factor K + 1, on the contrary, a delay in the appearance of pulses occurs. Thus, the i-th pulse at the output of the phase-shifting unit 2 is at the time + i T |. sooner or later than the original division ratio, which shifts the time scale.

As soon as the number written in the reversible counter 4 is counted,

514

the output of the latter appears level o (fig. 4k), which returns the driver 1 1 to the initial state. At its output, a level O appears (Fig. 4 l), and the initial division ratio of the phase-shifting unit 2 (Fig. 4 n) is restored and the And 7 element is closed (Fig. 4 o). The correction value At is equal to

fi.t ± N.T.

where N is the number recorded in the n-most bits of the shift register j T is the pulse repetition period

at the output of the generator 1. In the second mode of operation, the device operates as follows.

When leaving a stored time scale, ea, a tolerance limit for one of the Correction or Correction tires is given, depending on the exit sign, a command is issued (FIG. 5 g Correction-i). At the output of memory block 12, a correction code appears, and in the t-tad code bit contains information about the sign determined by the command given, and in the higher n-1 bits the correction value is equal to the allowable difference between the stored and reference time scales. At the same time, the command through the OR element 13 is fed to the shaper 4 (FIG. 5 d), at the output of which a single pulse is formed (FIG. Ze). This pulse is post-entered to the pre-recording input of the shift register 5, the correction code being rewritten from the memory block 12 to shift register 5.

At the same time, the impulse from the output of the former 14 through the inverter 15 pofig. 2

06

At the second input of an element 16 (FIG. 5), the first in-course of which contains level 1 from the output of the decoder 9. At the output of element 16 at a time equal to the pulse duration at the output of the former 14, level O appears ( 5 h). After the occurrence of 1 and at the first input of the imaging unit 10, the last pickup of the second pulse from a series of pulses at the second input (figure 5 and). In the future, the operation of the device is the same as in the first mode (figure 5 a, l,

Hj c).

Claims (1)

Invention Formula The device for the correction of the scale. time auth. No. 1095431, characterized in that, with the aim of increasing the correction performance with significant discrepancies in time scales, a block is introduced into it the memory, the OR element, the pulse shaper, the inverter and the second element AND, the positive and negative correction inputs of the device being connected to the two inputs of the OR element and two memory inputs of the same name, the outputs of which are connected to the corresponding parallel inputs of the shift register, connected by its preliminary recording input to the output of the pulse former and the inverter input, the output of the decoder is connected to the input of the single pulse former via the second coincidence element, the second input of which is connected to the output the inverter, and the output of the element OR is connected to the input of the pulse former. Fial P n SR TY 5Tg JITP JITP JITP GPRT. P MSH 5Tg tTr ,. 7g ... Gg 1. 5Гг., 5Тг woman m p and. but 5 tTr ,. 7g ... Gg 1. 5Гг., 5Тг woman m p and. Ch Ch .. m