SU840900A1 - Divider - Google Patents

Description

The invention relates to computing and is intended to divide the binary number number by the pulse method. A device for dividing is known, containing divisible and divisor counters, two additional counters, a controllable key, a switch of operating modes and a comparison circuit of codes recorded in the divider counter and an arrow from the additional counters Ш. The disadvantages of this device, designed for the division operation, performed after completing the input of the dividend and divisor numbers, are the loss of the original information after the division, as well as redundancy devices, due to the use of a two-counter comparison circuit that uses logical coincidence and anti-coincidences, the number of which is equal to the number of bits of these counters. The closest to the proposed technical entity is a divisional device containing counters of the dividend, the divider and the result of the first and second counters, the clock pulse generator tzj. The drawback of the device is hardware redundancy caused by the use of two schemes for comparing the codes of the dividend and the division of bodies with the codes of two additional counters that form two controllable frequency dividers. The purpose of the invention is to simplify the device. . The goal is achieved in that the device for dividing, containing counters of the dividend, divider and result, the first and second counters, a switch, two controllable keys, two forcing pulses, a trigger and an AND element are entered, with the first fixed contacts nepBojR and the second groups the switch is connected respectively to the inputs of the dividend and device divider, the fixed contacts of the first and the third groups of the switch are connected to the output of the first control key, the second fixed contacts of the second and fourth groups of the switch are from the output the house of the second controlled key, the first inputs of the first and second controlled keys are connected to the device clock input, the counting inputs of the dividend counter and the first counter are connected respectively to the moving contacts of the first and third switch groups, the counting inputs of the splitter counter and the second counter are connected respectively to the moving the contacts of the second and fourth switch groups, the transfer outputs of the divisible counter and the first counter are connected to the inputs of the first and second drivers, respectively c, the output of the first pulse generator is connected to the second input of the first and third inputs of the second pulse shaper output of the second pulse driver with the first input of the element I and the fourth input of the first controlled key, the output of the trigger, the fifth input of the first controlled key and with the counting input of the result counter, the bit outputs of which are the output of the device result, the sixth input of the first controlled key is the input of the beginning of the device, the element output nta AND is connected to the second input of the second controlled key, the transfer outputs of the divider counter and the second counter are connected respectively to the k and J - trigger inputs. In addition, the control key contains a trigger, an OR element and two AND elements, while the trigger is connected to the first input of the OR element, the second input of which is connected to the output of the first AND element, and the output to the first input of the second And element, first through the sixth inputs the control key is connected respectively to the second input of the second element, And, 3, To the trigger inputs, the first and second inputs of the first element And, and R - the trigger input, the output of the second element And is the output of the controlled key.

FIG. 1 is a functional diagram of the proposed division device in FIG. 2 is a controllable key diagram; in fig. 3 - timing diagrams illustrating the operation of the elements of the device. .

The proposed device for dividing comprises a divisor counter 1, a divider counter 2, a result counter 3, first and second counters 4 and 5, a switch 6, controllable keys; 7 and 8, shapers 9 and 10 pulses, trigger 11, element 12, divisible input 13, divider input 14, clock input 15, calculation start input 16. The control key scheme contains a trigger 17, an element OR 18, elements AND 19 and 20.

The device for dividing works as follows.

In the initial state, the switch of 6 operating modes sets to in the first position. Counters 1-5

and trigger 11 is reset to O, keys 7 and 8 are open. Initially, the numbers of pulses corresponding to some digital codes of the dividend M and divider N are fed to the inputs of the dividend 1 and divider 2 counters through the operation mode switch b to the input 13 of the device for the dividend and input 14 for the divider (Fig. 3a, b, e). After filling the counters 1 and 2 with M and N numbers, the switch 6 of operation modes is shifted to the second position.

Claims (2)

Next, the division procedure is performed. The signal transmitted at the input of the device 16 for the Calculation command closes the first control key 7 and the inputs of the first counter 4 and the counter of the dividend 1 are connected to the clock input 15 of the device, through which a continuous sequence of clock pulses is applied (Fig. 3c, d, d g) Counters 1 and 4 are filled with clock pulses at the same time, and counter 4 lags behind counter 1 by M. At the moment counter 1 overflows, the first pulse generator produces a signal to open the first control key 7 and close the second 8 (FIG. 1, h) . Now the inputs of the second counter 5 and the counter 2 of the divider are connected to the signals of the clock input 15 of the device. Counters 2 and 5 are filled with clock pulses simultaneously, and the counter 5 lags behind counter 2 by N pulses. At the moments of overflow of counter 2, trigger 11 changes its state from 0 to 1, and during overflows of counter 5 it returns to state O, i.e. at the output of the second trigger 11, a periodic sequence is formed, impulses, the duration of which corresponds to the number of clock pulses equal to N (Fig. 3k). The second trigger 11 with signals 1 and O at its output periodically closes and opens the first control key 7. At the same time, counters 1 and 4 simultaneously fill in periodically incoming numbers of clock pulses equal to N through their first control key 7 (Fig. 3 d, g). At the moment of overflow of the first counter 4, the first controlled key 7 is disconnected and its subsequent switchings are stopped. The signal for the last unlocking of the key 7 is setting O at the output of the second pulse generator 10 at 1 at the output of the second trigger 11 (Fig. 3, and to). Thus, the periodic filling mode of counters 1 and 4 with W numbers is complete when the total number of clock pulses received at the inputs of counters 1 and 4 becomes equal to M. After the last unlocked first control key 7, the second control key 8 continues to hold closed until the moment; the last overflow of the second counter 5. The signal for editing the key 8 is the establishment of O at the output of the trigger 11 when O at the output of the second driver 10 pulses. At the end of the last impulse formed by the trigger ill, the division process ends (Figs. 3e, 3k). All auxiliary elements of the device are installed in their initial states: the keys 7 and B are open, the counters 4 and 5 and the trigger 11 are reset O. On the counters of divisible 1 and div 2, the numbers M and N are restored (FIG. 3 d , e, g, 3, and, k). The result of dividing P is the number of switchings of the trigger 11, counted by the result counter 7 and equal to the Managed keys 7 and 8 I implement with the help of logic elements and does not require large hardware costs. Invention 1. The device for dividing, divisible counters and the result, the first and second counters, characterized in that, in order to simplify the device, it comprises a switch, two control keys, two pulse drivers, a trigger and an AND element, with the first fixed contacts of the first and second The second switch groups are connected respectively to the inputs of the divisible and device divider, the second fixed contacts of the first and third switch groups - the output of the first control key, the second fixed contacts of the second fourth switch group - with the output of the second control key, the first inputs of the first and second control keys are connected to the clock input of the device, the counting inputs of the divisible counter and the first counter are connected respectively to the moving contacts of the first and third switch groups, the counting the inputs of the splitter counter and the second counter are connected respectively to the moving contacts of the second and fourth switch groups, the transfer outputs of the divisible counter and the first counter are connected to the inputs of the first and second pulse formers, respectively, and the output of the first pulse shaper is connected to the second input of the first and third third pulse formers , the output of the second pulse shaper is with the first input of the element AND and the fourth input of the first controlled key, the output of the trigger is connected to the second The input of the AND element, the input of the first controlled key and the counting input of the result counter, the bit outputs of which are the output of the device, the sixth input of the first controlled key is the input of the device’s start of calculation, the output of the AND element is connected to the second input of the second the controlled key, the transfer outputs of the splitter counter and the second counter are connected respectively to K and 3 to the trigger inputs. 2. A device according to claim 1, characterized in that the control key comprises a trigger, an OR element and two AND elements, wherein the trigger output is connected to the first input of the OR element, the second input of which is connected to the output of the first AND element, and the output is from the first input of the second element And the first through the sixth inputs of the controllable key are connected respectively to the second input of the second element I, 1, to the trigger inputs, the first and second inputs of the first element I and R to the input of the trigger, the output of the second element I is the output controlled key. Sources of information taken into account in the examination 1. The author's certificate of the USSR 455342, cl. G 06 F- 7/52, 1974. 2, USSR Copyright Certificate No. 615477, cl. G 06 F 7/52, 1976 (prototype). / J0Л 0JiOkii J / V Lj HZ / g r / / 50J L Lj .J Ti Bbtxod F / 7 i / WITH / f i /. 2 / ( 20