SU892675A1 - Clock pulse generator - Google Patents

Description

() CLOCK PULSE GENERATOR

The invention relates to pulse engineering and can be used in automation and computational technology. Known pulse generator. sequences, containing a paraphase master oscillator, a synchronization unit, executed on triggers and logic gates of the NAND, frequency divider, consisting of a trigger and a coincidence element p. However, this generator has limited functionality, since it forms only two phases of pulses. The closest in technical essence to the invention is a clock pulse generator containing a master oscillator made on the first multivibrator, the outputs of which are connected via pulse shapers to the bus bars of the phase former on the push-pull shift register, and a synchronization device performed on the second multivibrator whose input is connected to the output of the delay device, and the output to the control input of the key, the outputs of which are connected between the power source and the bus the master oscillator, and the input of the delay device is connected to the installation bus of the initial state of the phase shaper performed on shift register 2. However, in a known generator, when power is connected to the multivibr: the oscillator does not start immediately, but after a transient, resulting in the first pulses may be distorted in amplitude and duration, which will lead to distortion of the output pulses and reduce the reliability of the generator. In addition, in the generator, only one series of clock phases shifted relative to each other is removed from the output and it cannot operate in continuous mode, producing a continuous sequence of clock signals shifted relative to each other.

The purpose of the invention is to increase reliability and enhance functionality.

The goal is achieved by the fact that a clock generator containing a master oscillator, the output of which is connected to the input of the pulse former, a synchronization unit, a unit for shaping the phase shift of the pulses, is connected in series with the HE element, the OR element and the trigger whose output is connected to a setup input of a unit for forming a pulse shift in phase, the information input of which is connected to the output of the synchronization unit, the first input of which is connected to the output of the pulse former, and the second The second input is connected to the input element of the NOT, while the second input of the trigger is connected to the last output of the unit to form a phase shift of the pulses.

The drawing shows a functional diagram of the generator of clock pulses.

The clock pulse generator contains a master oscillator 1, a pulse shaper 2, a synchronization block 3, a block k for generating a pulse offset in phase, a NOT element 5 element OR i6, a trigger 7. The synchronization block 3 can be performed, for example, on a trigger 8 and the AND element The unit C may be performed, for example, on the counter 10 and the switch 11. The drawing also shows the start bus 12 and the mode select control bus 13.

The clock generator operates as follows.

The master oscillator 1 generates a pulse sequence, the pulse shaper 2 generates a pulse sequence with the necessary parameters of pulses: duration, fronts, amplitude. From the output of the imaging unit 2, the pulse sequence is fed to the input of the synchronization unit 3, which serves to lock (synchronize) the pulses from the output of the imaging unit 2 to the asynchronous trigger pulse on the bus 12 in step mode.

In the continuous mode of operation, the bus 13 is supplied with the level of a logical unit, which is fed to the input of the element OR 6, and from there to the input of the installation of the trigger 7 to the zero state. The trigger 7 is in the zero state and does not interfere with the operation of the counter 10.

Bus 12 is supplied with a logic one level. The trigger 8 by the falling edge of the signal from the output of the imaging unit 2 is set to one and does not prevent the pulses from passing through the element 9. From the output of the element 9, the pulse sequence goes to the information input of the counter 10. Under the action of the falling edge of these pulses, the counter 10 switches. At the outputs of counter bits 10 under the action

0 input pulses set different combinations depending on the number of pulses received at the input.

from the output of the element And 9, the pulses go to the information input of the switch 11, to the control inputs of which signals are received from the bits of the counter 10.

Depending on the combination on

The 0 control inputs of the switch 11 receive a pulse from the information input of the switch 11 to one of it. exits. At the outputs of the switch 11, alternately shifted from 5 to each other clock pulses C, SL, .. S. |, then the process repeats again, first appears

Phase C signal, then Cn, etc. . This is how a generator works in continuous

mode. When fed to the bus 13 of zero potential, the generator is transferred to the stepping mode. The trigger 7 under the action of the clock pulse of the last phase switches to a single

condition. The signal from the trigger output 7 is fed to the input of the installation of the counter 10. Under the action of the trailing edge of the counting pulse, the counter 10 is reset, with

which the pulses at the output of the switch 11 are not received. The clock generation is terminated by a pulse.

Claims (2)

last phase. When a negative pulse arrives on bus 12, the trigger 8 under the action of the trailing edge of the signal from the output of shaper 2 is set to the zero state preceding the appearance of pulse 5 of the first phase C, preventing the passage of pulses through AND 9 to the input of block k; A single signal from the output and the element NOT 5 is fed to the first input of the element OR 6 and to the zero input of the trigger 7. The trigger switches to the zero state, allowing the counter 10. The end of the trigger pulse on the bus 12, the trigger 8 switches to a single the state on the falling edge of the signal from the output of the imager 2, resolving the passage of subsequent pulses to the input of the block t. Counter 10 is switched. At the output of switch 1, phase C, Cn ... C pulses appear. With the arrival of the last phase C pulse (ij trigger 7 switches to one state. Counter 10 stops, the generation of clock signals stops. When the pulse reappears on bus 12, the generation process clock pulses C /, C ... Cu is resumed. Thus, in a step-by-step mode, the generator produces one clock pulse series under the action of pulses, starting from phase C and ending with Cj phase pulses. At this, the generation stops .V When fed to bus 13 single signal There is another possibility to control the generator. If at a single signal on bus 13 a potential of zero is applied to bus 12, the generator finishes the output of clock pulses by the phase at which this potential is applied. the potential for generation bus 12 is resumed from the next phase of the clock pulses. Thus, in the proposed pulse generator, in comparison with the known one, the stepping mode is implemented, which is necessary for us three equipment and debugging software 75 tools, as well as when troubleshooting, and continuous mode, required when the digital computer operates in normal operation. In addition, the possibility of programmatically suspending the series in restarting it from the next phase allows the devices to be interrupted at a specific location and resumed without distorting the operation algorithm, which provides control over the computational process, while in all operating modes and when switching from one mode to another clock pulses are not distorted, which leads to high reliability of the generator. The invention provides a clock generator, which contains a generator, the output of which is connected to the input of the pulse generator, a synchronization unit, a unit for shaping the phase shift of pulses, characterized in that, in order to increase reliability and expand functionality, the element NOT connected in series , the OR element and the trigger, the output of which is connected to the installation input of the unit for forming a pulse motor in phase, the information input of which is connected to the output of the synchronization unit tion, the first input of which is connected to the output of the pulse shaper and the second input coupled to the input of NOT circuit, said second trigger stroke is connected to the last output of the unit for forming the phase shift mpulsov. Sources of information, rintye taken into account during the examination 1. The author's certificate of the USSR, cl. H 03 K 3/6, 1973. 2. USSR author's certificate f, cl. H 03 K 1/06, 1972.