SU512577A1 - Switch Management Device - Google Patents

Description

the address inputs of the triggers of the counter 2, and also, including the zero output, through the element "OR 5 - with the input of the inverter 6 and with one of the inputs of the element" And 7; the element "AND 8, in which one of the inputs is connected to the output of the inverter 6, the other, connected to the second INPUT of the element" AND 7, - to the output 9 of the control signal of the addressable operating mode of the switches, and the output is connected to the inputs INSTALLATION "On the trigger lock 10; the element "OR 11, one of the inputs of which is connected to the output of the element" And 7, and the other connected to one of the inputs of the element "And 3" - to the output 12 of the control panel for cyclical operation of the switch; the element “AND 13, in which one of the inputs is connected to the output of the element“ OR AND, the other connected to the second input of the element “AND 3,” to the output 14 of the trigger signal, and the output connected to the installation input “1 trigger of the blocking 10; a decoder 15 in which one of the circuit inputs (coincidence of the zero channel is connected to IK output 1 of block 10 trigger, the other inputs of all coincidence circuits are connected in a known manner to the output of counter 2, and output 16 receives the key control signals of the corresponding channels.

The operation of the switch with the control unit is explained in the timing diagram of FIG. 2

It is conventionally considered that after completion of work in one of the selected modes (when the signal from output 9 or 12 is removed) a reset pulse is formed in a known manner, which sets the trigger of lock 10 to the state "O" (Fig. 2a).

In the address mode of the switch, the control signal from output 9 will arrive at time ti (fig. 26) to one of the inputs of the element "And 7 and element" And 8. If the channel address from the channel address generator 4 is not supplied (fig. 2d), then from the output of the element "AND 7 through the element" OR 11 there will be no joint signal to the element "AND 13, allowing the release from the output 14 of the trigger pulse Tzap gs - 2 (Fig. 2d). The trigger 10 will not change its state "O (Fig. 2a)" and, at the output 16 of the decoder 15, the zero-channel key control signals will therefore not be generated (Fig. 2g). Control signals at the output 16 will not be generated even if the address of, for example, the channel "O comes from the driver 4. at time / 4 (Fig. 2d), i.e., when the element" And 13 is no longer - A start impulse arrives. If, following the channel address assignment “O from output 14, arrives at time 5” (fit. 2 (5)), the trigger pulse Tzap e - t, then the trigger 10 will go to the state “1” (FIG. 2a), and output 16 The decoder 15 generates (Fig. 2g) a key control signal of the channel "O (as stipulated, the channel address" O of the driver 4 is not fed to the counter 2, which, as is known, is not in the initial state

prohibits the output “About the decoder 15). When at the time tj (fig. 2d) the channel address O is removed, then the formation, iys at the output of the element "And 8 pulse by its front

5 (Fig. 2e) will set the trigger 10 to the initial state (Fig. 2a), and the output of the key control signal of the 1 channel "O will be blocked, en (Fig. 2g). From the above description, it follows that the device in the address mode eliminates the uncertainty of the control of the zero channel (the channel "O is formed at the time ty, when both the signal of the address mode and the channel address" O and the start signal are shown in Fig. 26, 2d, 2e - works. switch).

5 In addition to this, in the initial state (after energization) the switch is protected from interference, because at the moment ti (Fig. 2e), at the output of the element "And 8 a pulse is formed, which by its front will establish a trigger 10

0, the position is "O (Fig. 2a), a prohibiton signal will be sent to one of the inputs of all the coincidence circuits of the decoder 15, and the output of the switch's key control signals will not be generated at the output 16 (Figs. 2g, 2c and 2i). AT

5 moment / 8 can be given the channel address “1 (Fig. 2d), which will set the triggers of the counter 2 to the appropriate position and allow passage through the element“ And 13 at the time tg (Fig. 2e) of the starting pulse Tzap

0 Trigger W goes into state "1 (fit. 2a) and lifts the ban on the generation of control signals by channel keys, including the key dropping" 1 (Fig. 2h) until / and when the feed of the channel address "1 ( Fig. 2d). Finally, at the time / 12, the channel address will be formed π, and at the time / 13, when the trigger pulse Tzap / 14- / 13 (Fig. 2e) arrives, the output of the key 16 at the output 16 of the decoder 15

0 channel "n (Fig. 2m). Subsequently, after the removal of the channel address n at the time of / 15 (Fig. 2d), the channel key management can be continued in the sequence defined by the operator or by the program defined.

When the switch operates in cyclical mode, the control signal from output 12 will be sent at the moment / 16 (Fig. 2c) to one of the high speeds of the AND 3 and (through the OR 11) element

0 "And 13. At the moment of tn (Fig. 2d), the impulse Tzap / 18 - / 17 from output 14 sets the trigger 10 to the position" 1 (Fig. 2a) and starts the master oscillator 1, from the output of which the clock pulses will start to arrive at the counting

5 start input counter 2. At the output 16 of the decoder 15, the key control signals of the switch channels will be formed sequentially in time. At the time of the / 17 (fig. 2a), the first channel is connected to the common output at the time. ДГ1 / | 9- / п, in the timeout (fig. 2i) - ", the channel at the time D7" / 21- - - / 20 , at the moment / 21 (fig. 2g) - the zero channel for the time AG / 22 - / 2i, etc. (with a constant frequency of clock pulses

5 connections of each channel to the common output are the same, i.e. A7i ... D7.1 Ago). Switching channels in the cycle will occur until at the moment of 4z (Fig. 2e) a reset pulse Tcbr 44-tza from output 17. formed in a known manner, installs (Fig. 2a), for example, through the element "OR 18 trigger 10 to position "O" and prohibit the operation of master oscillator 1. From the description of the operation of the device in cyclic mode, it is clear that it eliminates the uncertainty of control of the zero channel In the initial state, at the time tif, (Fig. 2c) to one of the circuit inputs the coincidence of the null kaial of the decoder 15 is inhibited (Fig. 2a) and at the exit e 16 is not formed key control channel signal "D (FIG. 2g). In addition, according to the received condition, the trigger 10 will change to the initial state when the operation mode is changed, and the prohibition signal, intermittently, of the zero channel of the decoder 15, will be fed to one of the inputs of the other channels, therefore, output 16 will not be generated channel key control signals (Fig. 2g, 2d, 2i) in the time interval from 16 to / 17. Consequently, this device, even in cyclic mode, ensures the noise immunity of the switch from the moment the power is supplied and the mode select signal to the moment the control signal is received.

Claims (2)

1. The control device of the switch, containing; its counter, the inputs of which are connected to the output of the master oscillator, and the output of the address driver, and the outputs are connected to the inputs of the decoder, characterized in that, in order to eliminate the unauthorized control of the zero channel of the switch, the blocking trigger, elements "OR," And and the inverter, and the address driver outputs through the element "OR are connected to the input of one element" AND and additionally through an inverter to the input of the second element "AND, and the other inputs of the elements" AND are connected control bus address operation mode switch, wherein the output of one element "and connected to the input of the installation “About the blocking trigger through the element“ OR, another input (of which is connected to the reset spike, and the output of the second element “AND is connected to the installation input“ 1 trigger lock through the element “OR, the other input of which is connected to the cyclic mode control bus, and the And element, the other input of which is connected to the start bus, and the output of the 1 blocking trigger is connected to one of the inputs of the coincidence circuit of the decoder zero channel. 2. The device according to claim 1, characterized in that, in order to increase the noise immunity, the input of the zero channel coincidence circuit input connected to the output 1 of the blocking trigger is connected to the corresponding inputs of the coincidence circuits of other channels. f8 / 7 5 mi-rLJ but  I I I I I I g .J 4 I rr 1Z 1S 1 Jum .- (i-.Ji j i.j Lii-t tj. j, -1 g j fs. w / iZhggii- iK tZ3 Zt EL J-L.LL..n.UT "W yy