SU1283952A1 - Pulse shaper - Google Patents

Abstract

The invention relates to computational and pulsed techniques and can be used in discrete automation devices as a pulse shaper with an adjustable delay relative to the trigger signal and with an adjustable number of pulses. The aim of the invention is to expand the functionality. In order to achieve this goal, an element 15, a key 16, a second toggle register 17, a comparison block 18 and a counter 19 are entered into the pulse shaper. In addition, the pulse forwarder contains two D-flip-flops 1.2, RS-flip-flop 3 , a group of 4 elements And 4, the distributor 8 clock pulses, the generator 9 clock pulses, the first toggle register 13, the switch 14. The introduction of the above blocks: allows you to provide a discretely adjustable delay of the generated pulses relative to the starting of the starting signal and the number of impulses generated pulse series. 6 cl. § (L s

Description

K9

sc

00

f

О1 ND

The invention relates to computing and impulse technology and can be used in discrete automation devices as a pulse shaper with an adjustable delay relative to the trigger signal and with an adjustable number of pulses.

The purpose of the invention is the expansion

PU elements A, outputs 5 and 6 of a device for connecting a start button, input 7 of a device for applying pulses of an asynchronous random sequence, distributor 8 sync pulses, generator 9 of sync pulses, outputs 10 of a device from which a series of pulses distributed in time is removed, outputs 11

O and 2 device functionality, from which ANDA elements are removed, device 5 and 6 outputs for connecting a start button, device 7 for supplying pulses of an asynchronous random sequence, valve 8 clock pulses, generator 9 clock pulses, device 10 outputs from which a series of pulses distributed in time is taken, outputs 11

and 2 devices that are being filmed

VA by providing a discretely adjustable delay of the generated pulses relative to the trigger signal and adjusting the number of the generated pulse series.

FIG. 1 shows a block diagram of the device; in fig. 2 - key scheme | in fig. block diagram of toggle registers; in fig. 4 - comparison block structure; in fig. 5 shows time diagrams of the device in the mode of pulse shaping relative to the triggering signal, with

the key position, corresponding to the switching of its first output with the first input, the second output with the third input, and the third output with the fifth input (key position in figure 2); code (K men 5 installed on the first toggle register that determines the number of the last (hectare) of the generated pulses of a single series; code installed on the second toggle register that determines the delay in the beginning of the formation of pulses at the outputs of the device (10), (11) and (12) with respect to the triggering signal on K half-cycle operation of the syncro-; splitter pulses (8); in Fig. 6, time diagrams of the device operation in re; Formation form K of series distributed over the device outputs (10)

pulses, when the key is in position, the corresponding output of the distributor 8 is synchronously switching its first output with the second input, the second output with the fourth input, and the third output with the sixth input; the code set on the first toggle register, which determines the number of the last (t-th) of the generated pulses in the last K-series; codec 0 installed on the second toggle register, which determines the number of pulse series formed at the outputs of the device (10).

The pulse shaper contains D-flip-flops 1 and 2, RS-flip-flop 3, group 50

55

The pulses are connected to the C input of the first D flip-flop, the D input of which is connected to the first inputs of the And 215 elements; the first output of the first D-trigger 1 is connected to the second inputs of the And 21 elements, the outputs of which are connected to the outputs of the device 10 and connected to the information inputs of the 4-terminal 14, to whose address inputs are connected the outputs of the first toggle register 13, the output of the RS flip-flop, is connected to the first input of the element 15 and the second and third inputs of the key 16, the n-th output of the distribution

0

single discretely alternating pulses, discretely adjustable in duration, first toggle register 13, switch 14, AND 15, key 16, second toggle register 17, comparison block 18, counter 19, device 20 input to set the counter to O, and elements 21 groups 4, toggle switches 22 toggle registers 13 and 17, elements 23 of the equivalence of the comparison block 18, a multi-input element AND 24 of the comparison block 18, an element NOT 25 of the comparison block 18.

Moreover, the output of RS-flip-flop 3 is connected to the S-input of the second D-flip-flop, the output of which is connected to the R-input of the first D-flip-flop and the first R-input of RS-flip-flop 3, the outputs of the first D-flip-flop 1 are connected to two opposite-polar outputs driver, D-input of the second D-flip-flop 2 is connected to the common bus, inputs 5 and 6 of the shaper for connecting the start button are connected to the second R- and W-rs of the RS-flip-flop 3, respectively, input of the shaper for pulsing the asynchronous random sequence is connected to the first S-BXO- ds RS flip-flop 3, generator output 9 syn Pulses connected to the input of the distributor clock pulses, the outputs of which are connected to the third inputs of the n elements And 21, and the first

five

0

0

five

pulses connected to the C input of the first D-flip-flop, the D-input of which is connected to the first inputs of the n elements And 215 first output of the first D-flip-flop 1 is connected to the second inputs of the n elements And 21, the outputs of which are connected to the outputs 10 of the device and connected to the information inputs to the 4-terminal 14, to the address inputs of which are connected the outputs of the first toggle register 13, the output of the RS flip-flop, is connected to the first input of the element 15 and the second and third inputs of the key 16, the n-th output distribution

312

doln., p 8 sync pulses with 1 {un with the second input of the element I 15, the output of which is connected to the counting input of the counter 19, the input of the zero setting which is connected to the additional input 20 of the device, the outputs of the counter 19 are connected to the first information inputs of the comparison unit 18 the second information inputs of which are connected to the outputs of the second toggle register 17, the direct and inverse outputs of the comparison unit 18 are connected respectively to the first and sixth inputs of the key 16, the fourth and fifth inputs of which are connected respectively to the direct and inverse outputs of the switch 14, the first output of the key 16 is connected to the D-input of the first D-flip-flop 1, the second output of the key 16 is connected to the control input of the comparison unit 18, and its third output is connected to the C-input of the second D-flip-flop,

D-flip-flops 1 and 2 are designed to generate pulse synchronization of an input asynchronous signal with generator pulses 9, as well as to fix the start and end moments of the formation of pulse series at the device outputs 10 or single pulses with discretely adjustable device outputs 11 and 12.

RS flip-flop 3 is designed to connect a device operation start button, while inputs 5 and 6 of the device are connected to the second R- and S-inputs of RS flip-flop 3, and input 5 is connected to the contact closed with a common bus when the button is released , and input 6 - to the contact closed with a common bus when the button is pressed. The first S-input of the RS-flip-flop 3 is connected to the input 7 of the device, intended for supplying trigger pulses of an asynchronous random sequence.

A group of elements And 4 is designed to form a pulse series of distribution in time over the outputs 10 of the device pulses by combining signals from the outputs of the distributor 8 sync pulses arriving at thirds of the inputs of elements And 21 of group 4, and control signals arriving at the first and the second inputs of the elements AND 21 of group 4, respectively, from the first output of the key 16 and the first output of the D-flip-flop 1.

24

Distributor 8 clock pulses are designed to distribute the pulses coming from generator 9 in time over n outputs, depending on the pulse number 1, ..., n. Distributor 8 is a standard element of pulsed and computing technology.

The sync pulse generator 9 is designed to form a continuous sequence of sync pulses. The output of the generator 9 is connected to the input of the distributor 8 clock pulses.

The first toggle register 13 is designed to set the number of single-point or last of the generated series of pulses distributed over the outgoing 10, as well as to specify a discrete adjustment of the duration of the single device generated at the outputs 11, and 12; pulses. The outputs of the first toggle register 13 are connected to the address inputs of the switch 14. The toggle registers 13 and 17 are elements for recording, storing, and issuing code information, toggle switches 22 are used as storage elements. Toggle registers 13 and 17 are shown in FIG. 3. The coding of each register bit is done by setting the corresponding toggle switch to the On position. or off

The switch 14 is designed to select the last (t-th) pulse in a single or last series formed, distributed over the outputs 10 of the pulse device, as well as to select a predetermined front of pulses with discretely adjustable duration, outputted from the outputs 11 and 12 of the device. The information inputs of the switch 14 are connected to the outputs of elements AND 21 of the group, the direct output of the switch 14 is connected to the fourth, and the inverse to the fifth inputs of the key 16.

Element I 15 and its connections are intended to pass to the counting input of the counter 19 clock pulses from the p-th output of the distributor 8 only after the arrival of the trigger signal stored on the RS flip-flop 3.

The key 16 is designed to configure the device to work in one of

51283952

two modes: delay, the formation of pulses relative to the trigger signal or the formation of a given number of pulse series. The key 16 is a built-in toggle or switch type switch, for example, П2ГЗ-2ПЗН, ЦЭО, 360.016 ТУ, or any other similar switch for two positions of three on

com and 21 groups 4 - low potential, i.e. device outputs are not energized.

In the mode of delay in the formation of pulses relative to the triggering signal, when a negative edge of an asynchronous random sequence arrives at input 7, RS flip-flop 3 switches to state 1 and high potential from its

boards. The block diagram of the key 16 in the code arrives at the first input of the ale position corresponding to the first of the two listed operating modes 15 is shown in FIG. 2

The second toggle register 17 is pre-assigned to set the desired delay in the formation of pulses relative to the trigger signal or the number of generated pulse series. The outputs of the second tumbler rement And 15, allowing the passage of clock pulses from the p-th output of the distributor 8 to the counting input of the counter 19.

At the same time, the high potential of the RS-flip-flop 3 removes the forced initial setting of the D-flip-flop 2 to state 1, the silencing of the horn 17 is connected to the second infor-20 16 in this mode of operation

corresponds to that shown in figure 2. Therefore, in this case, a high potential from the output of the RS flip-flop 3 additionally via the key 16 is fed to 25 the control input of the comparison unit 18, ensuring its operation with a constant presence of the survey. The direct output of the comparison unit 18 through the key 16 is connected to the D input of the trigger I. The effect of races that occurs at the moment of recalculation of the counter 19 at the direct output of the comparison block 18 is compensated for by the D-trigger 1 due to the synchronization of the counter 19 the inputs of the comparison unit 18. Comparison unit 18 is designed to compare the current state of counter 19 with the state of the second toggle register 17. The direct and inverse outputs and the control input of the comparator unit 18 are connected respectively to the first and sixth inputs and the second

key output 16. Block 18 comparison

thirty

is a set of equivalence elements 23, a multi-input element AND 24 and an HE element 25, and the outputs of the equivalence elements 23 are connected to the inputs of the many corresponding to the one shown in FIG. Therefore, in this case, a high potential from the output of the RS flip-flop 3 additionally via the key 16 is fed to 25 the control input of the comparison unit 18, ensuring its operation with a constant presence of the survey. The direct output of the comparison unit 18 through the key 16 is connected to the D input of the trigger I. The effect of races that occurs at the moment of counting counter 19 at the direct output of the comparison block 18 is compensated for by D-trigger 1 due to the synchronization of the counter 19 element I 24, to one of the inputs 35 pulses from the n-th output of the distributor, and the recording of the results compared. from block 18 to D-thonger 1, the clock is produced from the first output of the distributor 8. When the state of the counter 19 reaches the value set on the second toggle register 17, from the direct output of the comparison block 18 to the D-flip-flop 1 and the first inputs of the AND elements 21 groups 4 through the key 16 will arrive positive potential, preparing trigger 1 to switch to state 1 and allowing switching elements AND 21 of group 4. With the arrival on

From the control input of the comparison block 18, the interrogation signal arrives, the output of the multi-input element AND 24 is connected directly to the direct output of the comparison block 18 and through the element NOT 25 with its inverse output. The structure of the comparison unit 18 is shown in FIG. four.

The counter 19 is designed to count the clock pulses from its p-th output of the distributor 8 through the I / 15 element, which determine, depending on the operating mode, either the delay in the formation of pulses relative to the trigger signal or the number of generated pulse series.

s

The device works as follows

In the initial position, the triggers 1 and 3 are in the state O, the trigger 2 is in the state I, the counter 9 is in the state O. At the output of the element

6

com and 21 groups 4 - low potential, i.e. device outputs are not energized.

In the mode of delay in the formation of pulses relative to the triggering signal, when a negative edge of an asynchronous random sequence arrives at input 7, RS flip-flop 3 switches to state 1 and high potential from its

And 15, allowing the passage of clock pulses from the p-th output of the distributor 8 to the counting input of the counter 19.

At the same time, the high potential of the RS-flip-flop 3 is removed from the forced initial setting of the D-flip-flop 2 to state 1, Pololchenie 16 in this mode of operation

0

corresponds to that shown in figure 2. Therefore, in this case, a high potential from the output of the RS flip-flop 3 additionally via the key 16 is fed to 5 the control input of the comparator unit 18, ensuring its operation with a constant presence of polling. The direct output of the comparison unit 18 through the key 16 is connected to the D input of the trigger I. The effect of races that occurs at the moment of counting the counter 19 at the forward output of the comparison block 18 is compensated for by the D-trigger 1 due to the synchronization of the counter 19 from a p-ny exit distributed

tel and a record of the results compared. from block 18 to D-thonger 1, the clock is produced from the first output of the distributor 8. When the state of the counter 19 reaches the value set on the second toggle register 17, from the direct output of the comparison block 18 to the D-flip-flop 1 and the first inputs of the AND elements 21 groups 4 through the key 16 will arrive positive potential, preparing the trigger. A switch 1 to state 1 and allowing switching elements AND 21 of group 4. With the arrival of the clock synchronization edge from the first output of the distributor B of synchronous 1 pulses to the C input of the D-flip-flop 1, this D-flip-flop switches to state I , but. match 1

signals at the inputs of the first element And 21 of the clutter 4 cause the appearance at its output of a 1-signal. On the negative front of the clock at the third input of the first element I 21

group 4, this element is switched, and the initial zero potential is formed at its output. The sequential occurrence of sync pulses at other outputs of the distributor 8 in a similar manner causes alternate switching of the remaining elements of AND 21 of group 4, which ensures the issuance of a series of pulses distributed in time over the device outputs 10 and arriving at the information inputs of the switch 14. There are binary signals on the address inputs of the switch - ny code of the channel address of the switch, dialed on the first toggle register 13. Thus, when a positive pulse appears at the output of the element 21 of group 4, the number of which It coincides with the dialed channel number of the switch 14, at the inverse output of the switch 14, a negative polarity pulse arises, the back gullance front of which goes through the key 16 to the C input of the D-trigger 2 and overturns this D-trigger to the 0 state. as D-INPUT of D-flip-flop 2 is connected to the common bus. This, in turn, causes the switching of the D-flip-flop 1 across the K input to the 0-state, which prohibits the switching of elements AND 21 of group 4 at their second inputs. At the same time, the RS flip-flop 3 will be prepared for switching to the 0-state on the first R-input. RS-flip-flop 3 is switched to the 0-state and the subsequent installation of a 1 p-flip-flop 2 with a low level potential from the RS-flip-flop 3 output occurs when a positive edge of the asynchronous sequence arrives at input 7. The device returns to its original The state and after resetting the counter 19 at the input 20 of the device waits for a new start at the entrance 7. The D-Trigger Ger 1 when the device is in operation is in the State 1 during the time from the leading edge of the sync pulse from the first output of the distributor 8 to the trailing edge of the sync pulse th outputs of the distributor 8 to the trailing edge of a binary code set in the first register 13 therefore tumbler i installing different binary codes to the register 13 is provided tumbler discrete adjustment of the duration of pulses generated da outputs 11 and 12 of the device,

o

five

0

five

which are the direct and inverse outputs of the D-flip-flop 1. This also sets the number of pulses in a single series, distributed in time over the device outputs 10 and coinciding in duration with the generator pulses. By setting different codes on the second toggle register 17, discrete adjustment of the delay in the formation of imguls relative to the triggering signal is performed by blocking the outputs 10-12 of the device from the moment the triggering signal arrives until the state of the counter 19 coincides with the code set on the second toggle register 17. The adjustment quantum is the cycle of operation of the distributor 8, and to delay the pulse formation on K of full cycles it is necessary to set the code K + 1 on register 17, since the moment of arrival of the charging signal is asynchronous with respect to the clock pulses from the p-th output of the distributor 8 arriving at the counting input of the counter 19. Time diagrams of the device operation in the delay mode of forming the pulses relative to the trigger signal for the case when the code is set on the second toggle register 17 register 13 is set code shown on. FIG. 5. With the proposed device, the device works in the same way as the known one.

In the mode of forming a predetermined number of pulse series, the position of the key 16 is the opposite of that shown in FIG. 2. When a pulse of an asynchronous random sequence arrives at input 7, RS-flip-flop 3 switches to state 1, and a high potential from its output goes to the first input of element And 15,. Allowing the passage of clock pulses from the p-th output of the distributor 8 to the counting input of the counter 19. At the same time, the high potential from the output of the RS-flip-flop removes the initial installation of the D-flip-flop 2 in the connection. This 1 and through the key 16 prepares the D-trigger 1 for D-input to switch to state 1 and allows switching of AND 21 group 4 elements .- With the arrival of a positive edge of synchronization from the first output of the distributor 8 to the C-input of the D-trigger t this trigger switches to state

0

0

0

five

on

1, and the assignment of 1 signals to the inputs of the first element I 21 of group 4 B1) causes the appearance of a signal at its output. Further operation of devices for the formation of pulses at outputs 10 - 12 is similar, except that the pulses from the direct output of switch 14 that occur when the number of the pulse generated at outputs 10 coincides with the code set on the first toggle register 13 does not stop the operation of the device, as in the previous mode, but through the key 16 to the control input of the comparison unit 18, thus, in each cycle of the device operation, the results of the comparison of the state of the counter 19 with the code typed in the second cabinet are polled re 1 7,

The cat and the current state of the counter 19 will reach the value of the code specified on the register 17, the negative signal from the inverse of the comparison block 18 through the key 16 is sent to the C-ACK 0 - trigger 2, the back positive front of which flips this trigger to the 0-state . Further work on returning to the initial state cxehttii is also similar, i.e. as a result of operation of the device in the mode of forming a predetermined number of pulse series at the outputs 10, a series of time-distributed outputs 10 of the device pulses in an amount corresponding to the code set on the second toggle register 17 are formed, and the number of pulses generated in the last series, will be determined by the code specified on the first toggle register 13, the installation of the code n on the first toggle register 13 is forbidden in this mode of operation, since due to the races occurring on block 18, taking into account the overlap of the moments oepec ieTa of the counter 19 and the polling of the comparison unit 18, it is possible unauthorized termination of the operation of the circuit. Timing diagrams of the device operation in the formation mode of a predetermined number of pulse series for the case when the code is set on the second toggle register 17, and the code is set on the first toggle register are shown in Fig.6. In the case of the proposed device

five

0

five

0

five

0

five

0

five

Analogous to the operation of a sinking device.

At start-up, the operation of the device is similar to that described, since the output of the RS-trigger 3 on the first contact closure when pressing and releasing the button connected to inputs 5 and 6 generates an asynchronous signal of the same polarity as at the start from entry 7.

Claims (1)

Invention Formula A pulse shaper containing a synchronous pulse generator, two D-flip-flops, RS-flip-flop, clock distributor 5 group of I elements, the first toggle register and switch, the RS-flip-flop output connected to the Z-input of the second B-flip-flop, the output of which is connected to The R input of the first D-flip-flop and the first R-input of the RS-flip-flop, the outputs of the first D-flip-flop are connected to two different output driver buses, the D-INPUT of the second D-flip-flop is connected to the common bus, the shaper inputs for connecting the button for- gusk connected respectively with the second R-and S-inputs of the RS flip-flop, the input of the generator for supplying pulses of an asynchronous random sequence is connected to the first S-INPUT of the RS-flip-flop, the output of the clock generator is connected to the input of the clock distributor, the outputs of which are connected to the third inputs of the n elements, the first output of the clock distributor is connected to the C-input of the first D-flip-flop, the D-input of which is connected to the first inputs of the n elements And, the first output of the first D-flip-flop is connected to the second inputs of the n elements And, the outputs connected to the output buses and connected to the information inputs of the switch, to the address input of which the outputs of the first toggle register are connected, so that, in order to extend the functionality by providing a discretely adjustable delay generated pulses relative to the triggering signal and adjusting the number of generated pulse series, the element I, the key, the second toggle register J the comparison unit and the counter are entered, the output of the RS flip-flop II1283952, 2 connected to the first input element of the toggle register, direct and in- and second and third key inputs, versus the outputs of the comparison unit, the nth output of the clock distributor is connected to the second input, the elelenen, respectively, with the first and sixth key inputs, the fourth and elemen And, the output of which is connected to the counter input of the counter, the input of the zero setting is connected to the additional bus of the device, the outputs of the counter are connected to the first information inputs of the comparison unit, the second information inputs of which are connected outputs the second (.lu4 Kb. K $ l.2 V R KffA.JS Fy toggle register, direct and inverse outputs of the comparison block respectively, the first and sixth inputs of the key, the fourth and fifth inputs of which are connected respectively to the forward and inverse outputs of the switch, the first output of the key is connected to the D input of the first D-flip-flop, the second output of the key is connected to the control input of the comparator, and its third output is with the C input of the second D-flip-flop. FIG. five Software to device codes (10) pulse 6