SU1203499A1 - Controlled generator of pulse sequences - Google Patents

Description

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The invention relates to digital computing and can be used in control systems.

The purpose of the invention is to expand the functionality by implementing a larger number of combinations of pulse sequences with the same amount of memory block.

FIG. 1 shows the functional diagram of the former; FIG. 2 shows the time diagram of the operation.

The former includes a pulse generator 1, a first counter 2, a first memory block 3, a switch 4, a group of 5 And elements, a delay element 6, a second counter 7, a second memory block 8, a comparison circuit 9, a third counter 10, And 11, element OR 12, inputs 13 of the initial installation, 14 start-up of the device, communication 15-23 between the elements of the device, outputs 24-26 of pulse sequences.

Fig. 2 shows signals 13 at the input of the device, 14 at the input of the device, at outputs 15 and 16, respectively, of the pulse generator 1 and delay element 6, 17-19 at the output of the first memory block (first three outputs), 20-22 at the output the second memory block (the first three outputs), 23 at the output of the element 11, the pulse sequences 24-26 at the outputs of the driver.

The device works as follows.

 Before operation, the counters are set to the zero state by an external Reset signal, arriving at the device input 13. Upon the arrival of an external control signal. Starting at input 14 of the device, oscillator 1 starts accelerating clock pulses 15.

The first counter 2 changes its state according to the front of the pulses of the generator 1. According to the code produced by this counter, a code combination of pulses (17-19, Fig.2) is selected from the corresponding cell of the first memory block 3, through which the first the inputs of the commutator 4 are fed to the first inputs of group 5 of the elements I. The second inputs of the elements AND of group 5 receive clock pulses, the front front of which is delayed by element 6

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delays by time equal to the sum of the switching time of the first counter 2 and the time for selecting a code combination from the first block of 3 pts. The introduction of the delay element prevents the distortion of the pulses at the output of the device. Thus, the formation of a pulse sequence is carried out during

10 of the first cycle. The cycle is completed if all the cells of the first memory block 3 are polled.

In the second cycle, the pulse sequence in several time positions differs from the first one. Consider the case when there are differences in the second and fifth temporal positions of the second cycle. If in the first cycle on the first three outputs

20 of the device for the second time position the code combination 101 was inserted, then in the second cycle for this position it is necessary to issue the code combination 010. Accordingly, if for the fifth time position in the first cycle the code combination was issued .111, then in the second cycle -points necessary to implement code combination 101.

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In the initial state, the second counter 7 is in the zero state and, accordingly, in the second memory block 8, the first cell is selected. The first part of the digits of this 5 ki is intended to store the code combination of the first interchangeable position (20-22, Fig.2), and the second part is to store the code of the time interval T1. The time interval code is applied to the first inputs of the comparison circuit 9, and the code combination to the second inputs of the switch 4, In this case, code 010 is stored in the first cell of the second memory block 8. The third counter 10, the outputs of which are connected to the second inputs comparison circuit 9, changes its state on the leading edge of the pulse of the generator S 1. In case of equal time code T1 recorded in the second memory block 8 and the code received from the output of the third counter 10, the comparison circuit 9

55 signals a comparison signal of a single level. This signal through the element 11 is fed to the control input 23 of switch 4, and

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Your combination from the output of the second memory block 8 (20-22, Fig. 2) through the second inputs of the switch 4 and through the group 5 of the elements I goes to the output of the device.

At the time of the end of the strobe signal 16, a voltage difference of 1-0 is created at the output of the element AND according to which the third counter 10 through the element OR 12 sets the zero state, and the second counter 7 changes its state. Thus, the third counter 10 begins to time the time interval T2, and the second counter 7 selects the second cell in the second memory block 8. In this case, the code combination 101 and the time interval code T2 are recorded in this

After the readout, the third code 1 counter is output to the device after the third counter 1 of this time interval.

Similarly, you can replace the code combination at any position in any cycle formed

pulse sequence. I

The device stops generating a pulse sequence if such a time slot code is recorded in the last used cell of the second memory block 8 that causes the third counter 10 to overflow. By the overflow signal from the output of the third counter 10, the generator stops generating pulses.

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Editor V. Petrash

Compiled by M. Silin

Tehred I. Lstalosh Proof-reader A. Obruchar

8417/51 Circulation 709 Subscription

BHMilinPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. d. 4 /; 3

Branch raill Patent, Uzhgorod, st. Project, 4

Claims (1)

A CONTROLLED PULSE SEQUENCE FORMER containing a pulse generator, three counters, a first memory block, an AND element, a group of AND elements, a second memory block, the input of the device’s initial installation being connected to the installation input at 0 of the first counter, the output and counting input of which are connected respectively to address input of the first memory block and to the output of the generator im-. pulses, the output of the Kth element of the And group is connected to the Kth output of the pulse sequence of the device, (K = 1, M, where M is the number of generated pulse sequences), the start input of the pulse generator is connected to the start input of the device, the output of the second counter is connected to to the address input of the second memory block, this is because, in order to expand the functionality by realizing more combinations of pulse sequences, it additionally contains a switch, a comparison circuit, an OR element, a delay element, and the input of the initial installation of the device is connected to the installation input at 0 of the second counter and to the first input of the OR element, the second input and output of which are connected respectively to the output of the And element and to the installation input at 0 of the third counter, counting input, information output and output the overflow of which is connected respectively to the output of the pulse generator, the first input of the comparison circuit and to the stop input of the pulse generator, the output of which through the delay element is connected to the first input of the And element and to the first inputs of elements of And group, the K-th output of the switch is connected to the second input of the K-th element of the group, the first information input of the switch is connected to the output of the first memory block, the output of the And element is connected to the control input of the switch and to the counting input of the second counter, the output of the number code the clock stroke of the second memory block is connected to the second input of the comparison circuit, the output of which is connected to the second input of the And element, the pulse code output of the second memory block is connected to the second information input of the switch. 'Tis