SU1182577A1 - Storage - Google Patents

Abstract

A STORAGE DEVICE containing memory blocks, the first group of registers, the first group of elements AND, the element OR, the pulse distributor, the delay element and the synchronization unit, one of the outputs of which is connected to the synchronization inputs of the registers of the first group, and the other inputs the first group, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the input of the delay element, the output of which is connected to the input of the pulse distributor, the outputs of which are connected to the inputs of synchronization and memory blocks, where the same inputs of the first group of registers are respectively combined and are information inputs of the device whose synchronization input is the input of the synchronization unit, characterized in that, in order to increase the information capacity of the device, elements of equivalence are entered into it, the encoder, the second group of registers, switches, second and third groups of AND elements, AND-OR element, NOT elements, clock counters whose counting inputs are connected to the outputs of AND elements of the second group, first inputs which are connected to the output of the I-GSHI element, the first inputs of which are connected to the outputs of the elements NOT, the inputs of which and the second inputs of elements AND of the first group are connected to the outputs of the equivalence elements, the outputs and the installation, inputs of clock counters are connected respectively to the first inputs and outputs of the blocks pa (O mti, the second inputs of which are connected to the outputs of switches, the inputs of which are connected to the outputs of registers of the first group, and the control inputs with the outputs of registers of the second group, inputs of which are connected to the outputs of the encoder, the inputs of which are connected to the outputs of elements AND of the first group, the synchronization inputs of registers to the second group are connected to the outputs of AS elements of the third group, the first inputs of which are connected to the output of the OR element, the second inputs of the elements of the second and third groups are connected to the outputs of the distributor pulses, the second inputs of the AND-OR element are connected to other outputs of the synchronization unit, the output of each register of the first group is connected to the first input of the equivalence element of the same name and to the second input after the equivalent element, the first input of the first equivalent element is connected to the output of the last register of the first group.

Description

eleven

The invention relates to computing., In particular, to storage devices, and can be used to register the code exchange of digital devices in logic analyzers, as well as when debugging digital computing systems.

The purpose of the invention is to increase the information capacity of the device.

FIG. 1 shows the functional scheme of the device; in fig. 2 - the same, the most preferred variant of each memory block implementation.

The device contains (figure 1) the first group of registers 1, block 2 synchronization, elements 3 equivalence, elements NOT 4, the element AND-OR 5, the first group of elements And 6, the encoder 7, the element IPI 8, distribute spruce 9 pulses, switches 10 , the second group of registers 11, the second 12 and the third 13 groups of elements I, counters 14 cycles, blocks 15 of memory and the first element 16 delays.

Each memory unit 15 contains (FIG. 2) a drive 17, shapers 18 and 19 of single pulses, a delay element 20, a demultiplexer 21, a shaper 22 of short pulses, and an address counter 23.

Registers 1 and 11 can be performed on microchips 585IR12,133IR13. The number of information inputs of the device is equal to ha (where m is an integer) and the number of inputs of each of the registers 1. The number of registers 1 in the first group of equivalence schemes 3, NOT elements 4, And 6 elements of the first group is N (where N is an integer), and the number of switches 10, elements 12, elements 13 and 14 counters and 15 blocks equals M (where M is an integer).

Counters of 14 clocks can be implemented on chips 133IE7, 533IE7, switch 10 - based on chips 533KP12. Circuit 3 equivalence can be performed on the IC 533SP1. The drive 17 can be built on the chip. 541RU2 and has (m + t) bits, where ha is the number of bits to register the analyzed code, t is the number of bits to register the time code.

The device works as follows.

772

Before starting work, all the registers and counters of the device are reset to the zero state, the valve 9 is set to the first position, and the valve (conventionally not shown) of block 2 is in the N-oe position, the cells of blocks 15 are reset.

The device is activated by applying 24 pulses to the input. When the first pulse arrives at the first of the outputs of block 2, a short-term single signal appears that goes to the clock input of the first of the registers.

1, ensuring the recording .in register 1 of information from inputs 25. The first of equivalence schemes 3 compares the codes from the outputs of the first and N-oro registers 1, the last one at the beginning of the work should be equal to 000 ... 00. If the scheme of equivalence 3 marks the equality of codes, then at its output: there will be a zero level preventing the passage through the first of the elements

And 6 single signal from the first of the other outputs of block 2, which will pass to the output of the element AND-OR 5, through its corresponding input, as at the second corresponding input

the unit level will operate from the output of the first of the elements NOT 4.

Under the influence of the second and subsequent synchronizing pulses, the information will record

the second, third, and so on registers 1 to K are CSOs inclusive, and then again into the first, second and so on i, since the unit signals will be generated by block 2 sequentially on the second, third, ..., Nhm,

again on the first, second and so on his exits. These pulses are passed successively at the output of the element AND-OR 5 and further through the first of

elements And 1 2 - to the input of the first

counters 14, which as a result .n counts N pulses (where n. N is an integer) while (K + 1) - from the equivalence schemes 3 does not mark the inequality of codes (where K is the remainder of d divided by N). The unit level from the output of (K + 1) -th scheme 3 equivalence will allow the transfer to the output of (K + 1) -th element And 6 pulsed

the signal from the (K + 1) output of block 2 and prohibits its transmission to the output of the AND-OR element 5, the pulse signal from the code of the first AND element 6 enters the inputs of the encoder 7 and the element OR 8, causing the output of the encoder 7 the binary code corresponding to its (K + 1) th input, and the output of the element OR 8 also a pulse signal. The code from the output of the encoder 7 is fed to the inputs of the registers M, and the pulse signal is fed to the inputs of the AND elements 13 and to the input of the distributor 9 through the delay element 16, the delay time of which is chosen to be equal to or longer than the pulse signal, as a result of which the pulse signal passes the output of the first of the elements And 13 and then goes to the input of the synchronization 1 1 and the first of the registers 11 The format coming from (K + 1) -th register 1. After the delay time of element 16, the pulse signal enters the input of the distributor 9 and shifts the output unit to the next direction. Under the influence of a negative differential in the first direction, the shapers 18 and 19 of the first memory block 15 are started and the zero cell of information received from the outputs of the first switch 10 and the first counter 14 is written. After the end of the recording in the first block; 15 by the memory by the signal. The end of the recording from its output resets the first counter 14, in the memory 15 block the status of the counter of address 23 is incremented by one. If after the next sync pulse (K + 2) -a scheme 3 of equivalence also notes an inequality, then 774 information will be written into the zero cell of the second memory block 15 of the second counter 14 (zero code) and from the output of the (K + 2) -th input register 1, and the state of the counter 23 of the second memory block 15 will increase by one. If (K + 2) -a and the following equivalence schemes 3 indicate equality of codes, the device functions similarly to that described earlier with the difference that the count of the number of ticks in which the unavailable input information is stored will be produced by the second of the counters 14. After the inequality of codes is noted in some tact, the recording of information from the outputs of register 1 and second counter 14 will be made into the zero cell of the second memory block .15 memory, and the state of its counter 23 will increase by one. As a result, the information will be recorded in the following order: zero, first, second, etc. Cells 15 from the first to the M-th are sequentially, which provides a logical organization of the mode of reading information from the storage device. In the proposed device, the number N of input information processing channels is more than the partial from the sum of time fj, drift of information into register 1, comparison time tTcp, registration decision time and ttp time, recording information into memory block 15 by the minimum value. time interval between two adjacent clock signals at input 25, i.e. , t + + ssr + rem Zap Number of registration channels is chosen large

, / 7t

/ t

A

Claims (1)

A MEMORY DEVICE containing memory blocks, a first group of registers, a first group of AND elements, an OR element, a pulse distributor, a delay element and a synchronization unit, some of whose outputs are connected to the synchronization inputs of the registers of the first group, and the other inputs to the first inputs of the AND elements of the first groups whose outputs are connected to the inputs of the OR element, the output of which is connected to the input of the delay element, the output of which is connected to the input of the pulse distributor, the outputs of which are connected to the synchronization inputs of the block memory, and the same inputs of the registers of the first group are respectively combined and are information inputs of the device, the synchronization input of which is the input of the synchronization unit, characterized in that, in order to increase the information capacity of the device, equivalence elements, an encoder, the second group of registers, switches are introduced into it the second and third groups of AND elements, AND-OR element, NOT elements, clock counters, the counting inputs of which are connected to the outputs of the AND elements of the second group, the first inputs of which are connected us to the output of AND-OR, the first inputs of which are connected to the outputs of NOT element, which inputs and the second inputs of AND gates of the first group are connected to the outputs of the elements of equivalence, with outputs and inputs of counters mounting bars are respectively connected to first inputs and the outputs! 3 memory blocks, the second inputs of which are connected to the outputs of the switches, the inputs of which are connected to the outputs of the registers of the first group, and the control inputs are connected to the outputs of the registers of the second group, whose inputs are connected to the outputs of the encoder, the inputs of which are connected to the outputs of the elements of the first group, the synchronization inputs of the registers of the second group are connected to the outputs of the AND elements of the third group, the first inputs of which are connected to the output of the OR element, the second inputs of the AND elements of the second and third groups are connected to the outputs of the pulse distributor, the second inputs of the AND-OR element are connected to other outputs of the synchronization unit, the output of each register of the first group is connected to the first input of the same element of equivalence and to the second input of the next element of equivalence, the first input of the first element of equivalence is connected to the output of the last register of the first group. ί