SU1555858A1 - Controllable frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating, issuing and processing digital information. The purpose of the invention is to increase reliability and efficiency by reducing hardware costs by organizing new functional connections, performing RS-type triggers 8, 11, and performing pulse key 1 with storing the control signal with an OR expansion on the control input. The device also contains the element OR 2, the counter 3 pulses, the elements AND-NOT 4.1-4.N, the elements AND 5, 6, 10, the trigger 7, the element OR-NOT 9, the pulse key 12 with the memorization of the control signal, the input bus 13, reset bus 14, mode control bus 15, control bus 16 and output buses 17 - 19. 1 sludge.

Description

The invention relates to a pulse technique and can be used in devices for generating, issuing and processing pulse information. 5

The aim of the invention is to increase reliability and efficiency by reducing hardware costs.

The drawing shows the electrical structural diagram of a controlled frequency divider.

The controlled frequency divider (UDM) contains a pulse switch 1 with control signal memorization, OR element 2, 3 pulse counter, η elements 15 AND-NOT 4.1-4. П, elements 5 and 6, first 7 and second 8 triggers, element OR NOT 9, element AND 10, third trigger 11, pulse switch 12 with a control signal memory, input 20 bus 13, reset bus 14, mode control bus 15, control bus 16, first 17, second 18, third 19 output tires.

The information input of the key 1 is connected to the bus 13, the first input is connected to the counting input of the counter 3, the first input of the Ibi element, the trigger start input 8, the first control input is connected to the output of the And 5 element, the inputs of which are connected to the outputs of the corresponding elements AND-NOT 4.1-4 .P, the first inputs of which are connected to the corresponding bits of the bus. 16, the second inputs are connected to the corresponding ³³ inverse bit outputs of the counter 3, the reset input of which is connected to the output of the OR element 2 and the reset input of trigger 11, direct and inject / ^ (1 version outputs of which are connected to the first inputs of the element OR NOT 9 and element And 10, the second inputs of which are connected to bus 15, the outputs are connected respectively to the reset input and trigger input of trigger 7, the inverse output of the latter is connected to the first reset input of trigger 8, the second input of which is connected to the first input of OR element 2 and reset bus 14 direct exit d connected to the second input ⁵ θ control key G, the second output of which is connected to the second input of the OR element 2 and the information input of the key 12, the first output of the latter is connected to bus 18, the second output> 5 is connected to the trigger input of trigger 7 and bus 19, input control is connected to the direct output of the trigger 11 and the second input of the element And 6, the output of which is connected to the bus 17.

The frequency divider operates as follows.

After switching on, the UDF should be initialized by applying a pulse to bus 14. At the same time, all bits of the counter 3, as well as triggers 7 and 8, are set to 0. If, when setting the initial state of UDF, level 0 is set on bus 15, then the outputs of the elements 9 and 10 there are levels 1 and 0, respectively, as a result of which the trigger 11 is set to 0. If, when the initial state of UDF is set, level 1 is set on bus 15, then the outputs of elements 9 and 10 have levels 0 and 1, respectively, as a result of which trigger 11 is set in 1. Original TATUS clock pulses on the bus 13 do not act on the tires 13, 14, 17-19, there are levels 0, on bus 15 has an arbitrary logical level on line 16 is given a binary code number K.

Suppose that there is level 0 on bus 15, and binary code is given on bus 16, for example, the number K = 3. At the same time, the outputs of elements 4.1 and 4.2, as well as the output of element And 5, have levels 0. Since both key control inputs 1 are levels 0, then after applying the clock pulses to bus 13, the first of them, in accordance with the rule of operation of the pulse key with the control signal, goes to the first output of key 1. As a result, the number 1 is written into counter 3, and the trigger 8 is set to 1. On the output of element 6, the pulse from the first output to yucha 1 fails, since the element 6 has a level 0 output from latch 11. As a result of switching in 1 trigger element 8 on the output 9 is set level 0, but the state of the flip-flop 11 does not change at the second input.

The next two clock pulses also pass from the GB bus to the first output of key 1 and increase the number in counter 3 to three, and also confirm the single state of trigger 8. Since counter 3 has a fixed binary code of the number '1555 “5”

3, then the levels 0 are set at the two least significant bit outputs of the counter 3, and levels 1 are set at the outputs of the elements 4.1 and 4.2. The level 1 is formed at the output of element 5 and the first control input of key 1. The fourth clock pulse passes from bus 13 to the second output of the key 1 (since at the time of its formation on the bus 13 at the first input of the control of the key 1 there is level 1) and then goes to the information input of the key 12. In accordance with the level O acting on the control input of the key 12, the pulse from the information input of this the key passes and its first output and formed on the bus 18.

In addition, the pulse from the second output of key 1 passes through element 2 and acts on the reset inputs of counter 3 and trigger 8, as a result of which all bits of the counter 3 and trigger 8 are set to 0 ^m . At the same time, at the first control input of key 1 and the output of element 9, the levels O and 1 are set, respectively, and the UDM returns to its initial state. Despite the fact that during the action at the information input of key 1 of the fourth pulse of the clock frequency, at the first control input of this key, the signal level changes from 1 to “O”, this pulse retains its duration at the second output of key 1 and is not formed on it the first output, which is due to the property of the pulse key with the memorization of the control signal. If the clock pulses continue to arrive on the bus 13, then the operation of the UDF in this mode is repeated as described.

Thus, if there is level 0 on bus 15, and a binary code of a certain number K is specified on bus 13, then after applying the clock pulses to bus 13, the UDM transmits every (K + 1) th clock pulse and, therefore, the division ratio of the UDM in this mode is (K + 1). On buses 17 and 19, levels 0 are saved in this mode.

Let there be a 1 ”level on bus 15 and a binary code, for example, the same number K = 3, on bus 16. At the same time, the outputs of elements 4.1 and 4.2 and the output of element 5 have levels ’’ О, and the direct output of trigger 11 is level 1. After applying the clock pulses to bus 13, the first one passes to the first output of key 1. As a result of this, the number ”1 is written into the counter 3, a pulse is generated on the bus 17, the duration and temporary position of which correspond to the first pulse of the clock frequency, and the trigger 8 is set to 1. Due to the switching of the trigger 8, the output of element 10 is set to level 0, however, the state of the trigger 11 does not change.

The next two clock pulses also pass from bus 13 to bus 17 and at the same time confirm the single state of trigger 8, and also increase the number in counter 3 to three. As a result of this, level 1 is set at the first control input of key 1. The fourth pulse of the clock frequency passes from bus 13 to the second output of key 1 and then goes to the information input of key 12 ”. According to level 1, which is valid at the control input of key 12, the pulse with the information input of this key passes to its second output, is formed on the bus 19 and enters the input due to which at 7 1.

trigger start 7, direct trigger output key control input level 1.

Also momentum

Key I moves I to the reset inputs of counter 3 and trigger 8, as a result of which all bits of counter 3 and trigger 8 are set to 0. In this case, at the first control input of key 1 and the output of element 10, levels 0 and 1 are set, respectively, and on the direct trigger output 11 saves level 1. Since by the time the fifth clock pulse arrives on bus 13 at the second control input of key 1 there is level 1, the fifth and all subsequent clock pulses pass from bus 13 to bus 19, confirming a single state of the trigger ^^ 7.

Thus, if there is level 1 on bus 15, and on binary 16, a binary code of a certain number K is specified, and the second | setting40 s

through the second element, after feeding the clock pulses to bus 13, the UDF allocates the first K clock pulses on bus 17, and on the bus 19 - clock pulses without the first K pulses ^! owls, i.e. (K + 1) th, (K + 2) th, etc. On bus 18, O level is maintained in this mode.

If on bus 15 a change in signal level _{t of the} signal from O to 1 occurs during frequency division, when a certain number О г М <К is recorded in counter 3, then this does not cause level changes at the outputs of the elements | 9 and 10, and, therefore, does not affect the state of trigger 11. Under the action of the K-th clock pulse, level 1 is formed at the output of the And 5 element and the first input of key 1 control, as a result of which the (K + 1) th clock pulse frequency passes from bus 13 to the second output of key 1 and then goes through key 12 to bus 18, and through element 2 2 to the reset inputs of counter 3 and trigger 8. As a result, all bits of the counter 3 and trigger 8 are set to 0, the output of the element stores level O, and the output _{3 of} element 10 forms level 1 “, which provides the installation of the trigger 11 in 1 and, therefore, changing the further mode of operation of the UDM. Despite the fact that during the action at the information input of the key of the 12th (K + 1) th pulse of the clock frequency at the control input of the key 12, the signal level changes from O to 1, this pulse retains its duration on bus 18 and is not formed on the bus 19, which is due to the property of the key 12. Further operation of the UDF is similar to that described in the allocation mode on the 17 K bus clock pulses.

Thus, if the voltage level changes from 0 to 1 on the bus 15 during the frequency division, when a certain number 0 <K is written in the counter 3, then the UDM operation mode changes only at the moment of completion of the current duty cycle, when the bus 18 is formed output pulse.

If on bus 15 a change in signal level 55 of the signal from 1 to 0 occurs at the moment when M pulses are already allocated on bus 17 (where то), then this causes changes in the voltage levels at the outputs. Elements 9 and 10, and therefore, does not influence on the state of trigger 11. Since after the action of the K-th pulse at the first control input of key 1 there is level 1, the (K + 1) -th clock pulse passes from bus 13 to the second output of key 1 and enters through the key 12 to the bus 19 and the trigger start input 7, as well as through the OR element 2 to the reset inputs of the counter 3 and trigger 8. In this case, trigger 7 is set to 1, and all bits of the counter 3 and trigger 8 are set to 0. As a result of switching trigger 8, level 1 is formed at the output of element 9, which causes triggers 11 and 7 to be sequentially set to 0 and, therefore, changing the further mode UDC works. Short-term switching to trigger 1 at the moment of formation of the output pulse on bus 19 does not affect the duration of this pulse, which is due to the use of pulse keys in the UDC with storing the control signal. Further work UDM is carried out similarly as described in the frequency division mode.

Thus, if on the bus 15 the voltage level changes from 1 to 0 occurs at the moment when AND pulses are already allocated on the bus 17, then the UDM operation mode changes only after all K pulses are selected, namely at the time of formation of the output pulse on bus 19.

Claims (1)

SUMMARY OF THE INVENTION A controllable frequency divider containing the first AND element, the inputs of which are connected to the outputs of the corresponding AND elements, the first inputs of which are connected to the corresponding bits of the control bus, the second inputs are connected to the corresponding inverse discharge outputs of the pulse counter, the counting input of which is connected to the first output the first impulse key with storing the control signal and to the first input of the second AND element, the output of which is connected to the first output bus, the second input to the direct output the first RS-type trigger and to the input - 1555858 control of the second pulse key with storing the control signal, the first and second outputs of which are connected respectively to the second and third output buses, the information input is connected to the second output of the first pulse key with storing the control signal, the information input of which is connected to the input bus, second trigger, third a trigger, the direct and inverse outputs of which are connected to the first inputs of the OR-HE element and the third AND element, respectively, the second inputs of which are connected to the mode control bus, the outputs are connected respectively to the reset input and to the start input of the first trigger, and an OR element, characterized in that, in order to increase reliability and economy by reducing hardware costs, a reset bus is introduced into it, the second and third triggers are RS-type, and the first pulse switch with storing the control signal is made at the control input with OR expansion, and its first 5th control input is connected to the output of the first AND element, the second control input is connected to the direct output of the second trigger, the trigger input otorrhea connected to the second output of the second pulse switch latched control signal, a first reset input - to the inverse output of the first flip-flop, a second input Throw ₁₅ ca - the bus reset, and to the first input of the OR gate, the second input of which is connected to the second output of the first pulse key storing the control signal, the output is to the inputs 20 of the reset of the pulse counter and the third trigger, the trigger input of which is connected to the first output of the first pulse key with storing the control signal.