SU1365356A1 - Code-to-pulse recurrence period converter - Google Patents

Abstract

The invention relates to computing and information technology. The aim of the invention is to spread the functional capabilities of the converter capabilities by extracting pulses of a given length. The converter operates in two modes: converting a parallel binary code to the inputs of block 6 of keys, v a pulse repetition period, and extracting pulses of a given duration. The converter contains elements AND 1.9-11, trigger 2, shaper 3 pulses, element OR 4, element AND-OR 5, block 6 of keys, subtracting counter 7, and element OR-NOT 8. 1 Il.

Description

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The invention relates to computing and can be used to convert parallel binary code during a pulse repetition period and to determine the duration of the pulses.

The aim of the invention is to enhance the functionality of the converter by imparting pulses of a predetermined duration.

The drawing shows a functional diagram of the Converter, which contains the third element AND 1, trigger 2, shaper 3 pulse, the element OR 4, the element AND-OR 5, block 6 keys, subtractive counter 7, the element OR-NOT 8 and the first 9, second 10 Quarter 11 elements I.

The Converter operates as follows.

The code conversion mode in the pulse repetition period is carried out when a zero signal is applied to the control input of the converter. In this case, the element And 1 is closed, the clock frequency enters the counting input of the counter 7 through the first element AND of the AND-OR element 5.

the front of the fifth pulse, the counter 1 is set to the zero state, a zero level appears at its lower-order direct output and a unit level at the inverse output. The output state of the element ORI-8 does not change. Unit levels at the inputs of AND 10 cause a single level at its output that permits key block 6 to write a number code to counter 7, after which the elements OR NOT HE 8, as well as 9, 10 and 4, and key block 6 are returned to their original state. condition. The conversion of the number to the pulse period is repeated.

When writing to the subtractive counter 7 the code of the number 001 (one) by the time

arrival of a common input pulse at the direct output of the low-order bit of counter 7 and at the output of the element ORI- NE 8, the potential of a single level is maintained. Therefore, the input pulse passes through the open element AND 9 to the output of the converter, and on the falling edge the counter 7 is set to the zero state, the element And 10 is triggered, and through the block 6 keys in

Suppose that in the initial state, in the counter 30 counter 7, the code of the number 7 is entered, the code of the number 101 (five), 001 is entered. Thus, the main clock input of the converter is empty, there are no input pulses, the output of the OR-HE element 8 and the outputs cops And 9 and 10 - zero levels.

When a pulse sequence converter arrives at a clock input, counter 7 begins to subtract one by one from a number code entered into it. At the end of the first pulse in the counter 7 there is a code, equal to four, at the end of the second - a code equal to three, at the end of the third - a code, two, at the end of the fourth - a code, equal to one.

When the code is equal to one, the direct output of the low-order bit of counter 7 is set to a single level, which enters the input of the element AND 9, and the zero levels of the direct outputs of the discharge of the counter 7 - at the inputs of the element OR NOT 8. At the output element SH-NE 8 sets a single level that blocks AND 9 and 10, the next fifth pulse of the input sequence passes through AND 9 to the output of the converter. On the back

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generating the code of the number 001 during the period following the output pulses.

When writing the number 000 (zero) to the counter 7, the And 9 element is closed with the zero level from the direct output of the low-order counter of the 7, and the unit levels from the output of the OR-NOT 8 element and the inverse output of the counter 7 through the AND 10 element and the 6 key block hold in counter 7, the code is the number 000. Thus, the converter converts the codes of numbers greater than zero in the period of repetition of pulses. With a zero code value, the output sequence is absent, while the output pulses have such a duration as the input pulses.

When a unit-level signal is applied to the control input of the unit, the first element AND of the AND-OR 5 element is closed, and the AND 1 element is opened. This state of the converter corresponds to the impulse latching mode, the duration of which corresponds to the duration specified by the code on the installation inputs of the converter.

at the moment of occurrence of a pulse at the control input of the converter, the trigger 2 triggers along the front of this pulse, opening the second element AND of the AND-OR element 5. At the same time, the clock pulses begin to arrive at the counter input 7 of the counter.

The fall of the pulse at the information input of the converter starts the shaper 3, at the output of which a short pulse appears. If this pulse coincides with the pulse at the output of the AND 9 element, it passes to the input of the AND 11 element, indicating that the input pulse duration corresponds to the code at the inputs of block 6. At the same time, the pulse from the output of the forcing 3 through the OR 4 element resets the trigger 2 to its original position and closes the keys of the block 6, writing the code into the counter 7.

The device is in its original state and prepared for operation.

If the pulse duration at the information input of the converter is greater than the duration specified by the code on the installation inputs, the occurrence of a pulse at the output of the element AND 10 through the element OR 5 resets the trigger 2 and closes the keys of the block 6 to write the code into the counter 7. This corresponds to the initial state of the converter, while at the output of the element And 11 information does not occur. At the end of the pulse at the information input, the initial state of the converter is confirmed by a pulse from the output of the formate - l-- 3.

Thus, the proposed device, in comparison with the known one, possesses advanced functional capabilities that allow, in addition to the function of converting the code to the pulse repetition period, to implement the pulse selection mode, the duration of which is given by the code supplied to the information inputs of the key block 6.

VNIIPI Order 6657/56 Circulation 928

Random polygons pr-tie, Uzhgorod, st. Project, 4

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Claims (1)

Invention Formula The code converter in the pulse repetition period containing the block 5 keys, whose information inputs are the converter inputs, the outputs of the key block are connected to the corresponding information inputs of the counter, direct, The 10 inverse low-order outputs and the direct outputs of all bits, except the low-order counter, are connected respectively to the first inputs of the first, second AND elements and the corresponding inputs of the OR-NOT element, the output of the OR-NOT element is connected to the second and the first and second inputs And elements, the output of the first element And is the first output of the converter, characterized in that,. in order to expand the functional. capabilities of the converter due to the selection of pulses of a given duration, the third, fourth AND elements, the OR element, the trigger, the pulse shaper and the AND-OR element are entered into it, the first inputs of the third AND element and the AND-OR element are combined and are the control input the converter, the second input of the third element I is the information input of the converter, the output of the third element I is connected to the clock input of the trigger and the input of the pulse generator, the output of the pulse former is connected to the first inputs of SLT and the fourth element and the second inputs of which are connected to the outputs, respectively, 40 of the second and first elements. AND, the output of the fourth element AND is the second output of the converter, the output of the OR element is connected to the control input of the key block and the input of the installation in O of the trigger, the output of the trigger is connected to the second input of the AND-OR element, the third and the quarter whose inputs are combined and are the clock input of the converter, the AND-OR element is connected to the counter input of the counter and the third input of the first element I. thirty Subscription