SU1359896A1 - Pulse-delay device - Google Patents

Abstract

The invention can be used in time delay control devices for pulmonary signals. The purpose of the invention — extending the functionality — is achieved by providing control of the delay time and expanding the range of the delay time. To do this, a device containing a bus 1 input signals, a bus 2 output signals, N-bit register 4 shift, elements And 6 and 12, triggers 8 and 10, the generator 11 clock pulses and n-bit counter 13, additionally introduced switch 3, the decoder 5 zero, the element And 7, block 9 comparison codes and bus 14 code sample delay time. The operation of the device is explained in the time diagrams provided in the description of the invention. 3 il. with SP 00 with 35 figl

Description

The invention relates to a pulse technique and can be used in devices for controlling the time delay of pulse signals.

The aim of the invention is the extension of functionality due to the possibility of controlling the delay time and extending the range of the delay time.

Fig. 1 is a block diagram of a device for delaying pulses; FIGS. 2 and 3 are timing diagrams explaining the operation of the device.

The device for delaying pulses contains bus 1 input signals, bus 2 output signals, switch 3, N-bit shift register 4, decoder 5 zero, element 6, element 7, trigger 8, block 9 comparison of codes, trigger 10, generator 11 clock pulses, element 12, p-razdny counter 13, tires 14 code selection time delay.

The output of the generator 11 clock pulses is connected to the first inputs of the elements 6 and 12, the second input of the element 6 is connected to the output of the second trigger 8, the input to the zero state of the first trigger 10 is connected to the bus 2 output signals and

the reset input of the counter 13, the counting input of which is connected to the output of the first element I 12, the output of the second element And 6 is connected to the clock input of the shift register 4., the information input of which is connected to the bus 1 of the input signals and the installation input of the first trigger 10 in the unit state , the lower bits of the bus 14 of the time delay selection code defined by the log N expression are connected to the control inputs of the switch 3, and the older ones defined by the expression Iog2 are connected to the first inputs of the code comparison block 9 and the inputs of the deshifter 5 zero, output to second is connected to the first input of the third element And 7, the second and third inputs of which are connected respectively to the output of the first trigger 10 and the output (Nl) -ro of the shift register 4, the output of the third element And 7 is connected to the installation input of the second trigger 8 in the unit the state and the second input of the first element And 12, the output of the bits of the counter 13 are connected to the second inputs of the block 9 of the code comparison, the output of which is connected

with the installation input of the second trigger 8 in the zero state, the outputs of the region of the shift register 4 are connected to the information inputs of the switch 3, the output of which is connected to the bus 2 output signals,

In FIG. 2, the following symbols are introduced; a is the pulse sequence on the input bus 1; b - clock pulses at the output of the generator 11; in - the signal at the output of the trigger 8; g - signals at the output of the element And 6; d and e - signals on the tires of the lower and higher bits of the code for selecting the delay time, respectively; g- - signal at the output of the decoder 5 3 - signals at the outputs 1,2, 3 ,,,, 11,; ,,, 16 bits of the register 4 shift; and - signal on the output bus 2,

Fig. 3 introduces the following notation: a is a pulse sequence on the input bus 1; b - so tovy pulses at the output of the generator 11; в - signal at the output of the trigger В; g - signal at the output of the element And 6; d - output signal (N-1) bit: shift register 4; e, g - signals on the buses of the lower and higher bits of the code for selecting the delay time, respectively; 3 - the signal at the output of the decoder 5 and - signal / 1 at the output of the element And 7; K - signal to the output element And 12; l - the signal on the trigger and 10; m - signals at the outputs of 1-5 bits of the counter 13; and - the signal at the output of block 9 comparison codes; about - the signal at the output of the N register and the output bus 2,

The device works as follows.

Before starting the operation after switching on the power source, the reset pulse sets the shift register 4, trigger 8 and 10, counter 13 to the initial state. shift and counter 13 are reset to the zero state.

When a pulse sequence device arrives on bus 1 and a delay time select code on bus 14, the device proceeds to its delay function, with STOh. it works in two modes: in the mode of small delays or in the mode of large

delays depending on the incoming code of the ppns. 14. The mode of small delays is determined by the presence of zeros in all major bits, and the mode of large delays - by the presence of all units in the lower bits and at least one unit in any higher bits of the delay time selection code.

Consider the operation of the device in the mode of small delays for N 16 and p 5. Suppose that bus 1 received a pulse sequence accompanied by a code for choosing the time of the delay, for example 00000 1010, (see Fig. 2). At the output of the decoder 5 zero, a low potential is established, closing element AND 7. At the output of element 6 there are clock pulses with a period T from the generator 11 clock pulses, as it is open with high potential from the output of trigger 8. The shift register 4 begins input pulse sequence. At the same time, 11 bits of shift register 4 are connected to the output bus 2, which corresponds to a given code per control, and their switch 3 inputs. On the output bus 2, after a time determined by the time 11 T, a pulse sequence appears which will be repeated. When other codes arrive, the delay time is within T,

 NT, where T is the period of the clock frequency.

When a device arrives on bus 1 of a pulse sequence and a code for selecting the delay time on buses 14, it contains a nonzero combination in the higher bits and all units in the younger ones, for example 10101 1111, the device operates in the large mode.

delays. At the same time, at the forefront is the 45th high level, which opens up

element AND 6, the first clock IMTU of the first pulse received at input 1 (see Fig. 3), trigger 10 is set to unit state i-j, at its output there is a high level, opening element AND 7 at the second input. At the first input, the AND 7 element will be opened by a high level from the input of the decoder 5 zero, since its inputs contain a nonzero combination. At the third input, the element 7. will be closed by a low level from the output of the (N-l) -ro bit of the 4 shift register, therefore the low level at the output of the element And 7

50

55

The pulse, at the output of which causes the pulse sequence to advance into the Nth bit (16 p) of the shift register 4 and enter it through the generator 3 to the output bus 2 of the device. The positive differential voltage appearing on bus 2 resets the trigger 10 and the counter 13 to the zero state, at the same time closing the elements And 7 and And 12. On the output bus 2, the input pulse sequence is closed. In this case, the delay time is determined by the expression

3598964

closes element 12 at the second output and the clock pulses from the generator 17 clock pulses to the counting input of the counter 13 do not pass, it is in the zero state. At the output of the element And 6 there are clock pulses from the generator 11 clock pulses, since the second Q input of the element And 6 is open with a high level from the output of the trigger 8. The 1-pulse sequence starts advancing the shift register 4 and manages to record during the (Nl) -T time into it, while to the output bus 2 is connected through the switch 3 N-bit of the register 4 shift. As soon as the first pulse of the pulse sequence progresses to the (H-1) -th bit (in our case, the 15th bit), a high level appears at its output, the opening element of AND 7 on the third; is a positive voltage drop, 25 causing the tilt trigger 8 to turn into a single state. At the same time, a low level appears at its output.

20

0

five

0

The incidence of the closing element AND 6 and the advancement of the pulse sequence through the shift register 4 is stopped. At the same time, a high level at the output of the element And 7 opens the element And, 12, at the output of which the clock pulses from the generator 11 of the clock pulses appear. The counter 13 starts counting pulses. This counting continues until the counter assumes a state equal to the higher-order code on the buses 14. At the output of the code comparison block 9, a positive voltage difference appears, causing the trigger 8 to return to the zero state. On his way out appears

0

five

the pulse, at the output of which causes the pulse sequence to advance into the Nth bit (16 p) of register 4 shift and enter it through the cogenerator 3 to the output bus 2 of the device. The positive voltage drop appearing on bus 2 resets the trigger 10 and the counter 13 to the zero state, with elements And 7 and And 12 being closed. On the output bus 2, the input pulse sequence is twisted. In this case, the delay time is determined by the expression

“D 16.T +

T 37-T.

The next input pulse sequence in high delay mode must be input. devices after issuing the entire previous pulse sequence, i.e. no earlier than time,; equal to 33. + (N-1) T.

When other selection codes arrive, the delay time is determined by the expression

N + 1 - e «d, (2 + N -.

about

Claims (1)

Invention Formula A device for delaying pulses, containing an N-bit shift register, bus, input and output signals, first and second triggers, first and second elements AND, n-bit counter, clock generator, the output of which is connected to the first inputs of the first and second elements And, the second input of the second element And is connected to the output of the second trigger, the input of the installation in the zero state of the first trigger is connected to the output signal bus and the reset input of the counter, the counting input of which is connected to the output of the first element And, the second output go-element AND-connected to the clock input of the shift register, the information input of which is connected to the input bus signals and the installation of the first trigger in a single state, characterized in that, in order to dissolve the functionality by providing the ability to obtain control of the delay time and increase the range of the delay time, the switch is entered into it 10 decoder zero, the third element AND, the code comparison unit, the input buses of the delay time code, with the digits of the delay time code defined by the expression logN, 15 are connected to the control inputs of the switch, and the higher ones, defined by the expression logZ, are connected to the first inputs of the code comparison unit. and the inputs of the decoder are zero, output 20 of which is connected to the first input of the third element And, the second and third inputs of which are connected respectively with the output of the first trigger and the output of the (N-1) -th bit of the register 25 shift, the output of the third element And is connected to the input of the installation of the second trigger in one state and the second input of the first element And, the outputs of the bits of the counter are connected 30 with the second inputs of the code comparison unit, the output of which is connected to the installation input of the second trigger in the zero state, the outputs of the bits of the shift register are connected to the information inputs of the switch, the output of which is connected to the output bus of the signals. tjmifl- / , 7) max fsr j): r M IIIIIIIIIIIHIIIIHIHIIIlllllllMllll Sh iiiiiiiiiiiiiii iiiiiiiiiiiii a- lgiishllishshlLL PP-P1JIL -TjL fig g Editor A. Dolinich Compiled by A. Titov Tehred L. Serdyukova Order 6163/55 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 Production and printing company, Uzhgorod, st. Project, 4 (pue.J Proofreader N.Korol