SU1256190A1 - Multichannel switching device - Google Patents

Abstract

The invention relates to automation and instrumentation technology and can be used in control and monitoring systems. The purpose of the invention is to reduce power consumption. The switch contains a n-bit binary counter 1, () of keys 2 and a decoder 6. Introduction of delay element 3, trigger 4, elements OR 5, element OR 7 with (ml) inputs, n parallel circuits 8, each of which includes element 9 the prohibition element AND 10 and the element OR 11, and (t-1) parallel circuits 12, each of which consists of trigger 13, elements OR 14 and 15, delay element 16, prohibition element 17 and element 18, simplify the device that is provided by the logic of the decoder 6, 2 table. 1 il. L7 (P S

Description

This invention relates to automation. ke and counter-measurement technology and can be used in systems of control and monitoring, for example, in command non-serviced devices.

The purpose of the invention is to reduce the power consumed by the Switch while maintaining the functionality of the device by simplifying the latter, which is provided by the logic of the decoder,

When decoding an n-bit binary code and implementing all the combinations of this code, the number of times the decoder M equals H-2. In Table. 1 shows the operation of the decoder DL, in table. 2 - operation of the decoder for inverse values of 5-8 code combinations.

- - iJlJL

Thus, the inverse values of 5-8 code packets stimulate the same decoder outputs as the direct values of 1-A code packets. This implies the possibility of building a decoder with the number of outputs m

M 2

fl -f

which and laid in os10

(New proposed device.

The drawing shows a functional diagram of a multi-channel switch.

The device contains a n-bit 15 binary counter 1, () keys 2j first delay element 3, first trigger 4, first element OR 5, de20

.X /: M

encoder popp inputs and w 2

the outputs, the element OR 7 s (t-1), the circuits, the n parallel circuits 8, each of which contains the first element 9, is forbidden, the first element is And, 10 and

 the second element OR 11, (t-1) parallel circuits 12, each of which includes the second trigger 13, the third 14 and the fourth 15 OR elements, the second, the delay element 16 delays, the second prohibition element 17 and the second element JJ8.

Binary n-bit counter 1, the counting and installation inputs of which are connected respectively to

35 informational 19, controlling 20 device inputs, 2 paraphase outputs, where n is the number of bits.

The first 3 delay element has

40 time delay, less than the period of the clock pulses arriving at the information input 19 of the device. The delay time on element 3 is determined by the time table 2 45 key 2 triggers.

Be1) vi 4 and second 13 triggers are RS-triggers, each of which has two separate installation inputs and is triggered by

50 pulses (voltage drops) of positive polarity.

The decoder 6, for example, with single-phase inputs has n inputs and m

 M 55 - 2 outputs, in the switch you -

move O is not used. The switching signals on the decoder codes can be gated. .

Thus, the inverse values of 5-8 code packets stimulate the same decoder outputs as the direct values of 1-A code packets. This implies the possibility of building a decoder with the number of outputs m

M 2

fl -f

which and laid in os10

(New proposed device.

The drawing shows a functional diagram of a multi-channel switch.

The device contains a n-bit 15 binary counter 1, () keys 2j first delay element 3, first trigger 4, first element OR 5, de20

.X /: M

encoder popp inputs and w 2

31

The second delay element 16 eliminates the concurrence of elements, in particular, of the triggers 13. The second polar delay element 16 does not change the signals to it nocTynaronpix. In total, the delay time on delay elements 3 and 16 does not exceed the period of the following clock pulses.

Multichannel switch works as follows.

The control signal at input 20 sets to zero the binary counter 1, the first trigger A and the second triggers 13 of all parallel circuits 12, except the trigger 13 of the first circuit, which through the first element OR 5 is set to one state, preparing the second element 17 prohibits the first circuit 12 from passing the switching potential to the key 2 from the first output of the decoder 6.

In the faultless operation of the device with the arrival of the first clock pulse at the counting input of the counter 1, a code is generated at its direct outputs that through the first prohibition elements 9 and the second elements OR 11 enters the decoder 6 inputs.

At the first output of the decoder 6, a switching potential appears through the third element OR 14. and the second element 17 prohibits the first circuit 12 to the corresponding key 2. At the same time, the signal from the first output of the decoder 6 through the element OR 7 s (ha-1) inputs , the third element OR 14 and the second element 17 of the prohibition of the first circuit enters the control input of the corresponding key 2, confirming that it has been triggered. A correction signal is generated along this circuit in the event of a false signal appearing at the jth output of the decoder.

The delayed signal from the output of the first delay element 3 through the fourth elements OR 15 of all parallel circuits 12 goes to the R-BXO of the flip-flops 13. At that, the flip-flop 13 of the first strand 12 returns to the zero state and the zero state of the flip-flops 13 of the other circuits is confirmed.

When the flip-flop 13 of the first circuit 12 returns to the zero state, the signal from its direct output through the second delay element 16 is set

five

 ABOUT

t5 20

five

five

P

0

five

0

five

1904

firing trigger 13 of the second circuit 12 into one state.

Then, the device operates similarly until the switching potential appears at the last mth output of the decoder 6, which is supplied to the corresponding key 2. The delayed pulse from the output of the first delay element 3 through the OR element 15 returns the second trigger 13 (t-1.) to zero state. In this case, a positive voltage drop across the second delay element 16 causes the first flip-flop 4 and the second flip-flop 13 of the first parallel circuit 12 to become one.

When installing the first trigger 4 in a single state, all the first 9 and second 17 elements of the pret are closed and all the first 10 and second 18 elements of I. are prepared for opening.

When the post-clock clock pulses arrive at the counting input, the counter 1- at the inputs of the decoder 6 through the first elements AND 10 and the second elements OR 11 of the parallel circuits 8 are fed the inverse code value, and the first and subsequent outputs of the decoder 6 are excited (Table 2) Switching potential from the output of the decoder 6 through the third element OR 14, the second element And 18, prepared for opening by the first 4 and second 13 triggers, goes to the corresponding key 2. The rest of the device is similar.

Claims (1)

Invention Formula A multi-channel switch containing a n-bit binary counter, the counting and installation inputs of which are connected respectively to the information and control inputs of the device, (2 -2) keys and also a decoder with n inputs, characterized in that in order to reduce the consumed the power switch, the first delay element is introduced, the input of which is connected to the information input of the switch, the first trigger, the R input of which is connected to the control input of the switch, the first OR element, the OR element with (ml) inputs and also parallel s circuits, each of which comprises a first element prohibition, the first AND gate and a second five SHS element, (ml). Parallel circuits, each of which includes a second trigger, a third and fourth OR elements, a second delay element, a second prohibition element and a second AND element, with the forward and inverse outputs of the i-bit counter connected respectively to the direct input of the first prohibition element and the first input of the first element AND, whose outputs through the second element OR are connected to the i-th input of the decoder, and the j-th output of the decoder is connected to the first input of the third element OR j-th parallel circuit and j to the input of the element OR with (t-1) input mi, the output of which is connected to the second inputs of the third element OR of all (t − 1) parallel circuits, the output of the third element I1Sh is connected to the first direct input of the second prohibition element and the first input of the second element I, the direct output of the second trigger is connected to the second direct the input of the second element of the ban, the second input of the second element And, Compiled by L. Bagn. Editor I. Shulla Tehred A. Kravchuk Proofreader M. Pojo Order 4836/57 Circulation 816. Subscription VNIIPI USSR State Committee on affairs of inventions and discoveries 113035,. Moscow, Zh-35, Raushsk nab, d. 4/5 Production and printing company, Uzhgorod, Project St. four . 56190b the output of each of which is connected to the control input of the corresponding key, and to the second input of the delay element, the output of which is connected to the 5th S input of the trigger (+1) -th parallel circuit, except for the delay element (t-1) -th circuit, output which is connected to the S-input of the second trigger of the first circuit through the first input of the first element SH and directly to the S-input of the first trigger, the direct output of which is connected to the inverse inputs of all the first and second prohibition elements, with the second inputs of all 15 first elements And with third the inputs of all the second elements AND, the second input of the first element OR is connected to the control input of the switch and with the first inputs of the fourth 20 OR elements of all (t-1) parallel circuits, except the first, the outputs of which are connected to the R-input of the second flip-flop of the corresponding circuit, to the second inputs of the fourth elements OR all 25 circuits connected to the output of the first delay element.