SU1339539A1 - Digital sequence forming device - Google Patents

Abstract

The invention relates to automation and computing and can be used to generate signals, presented in digital form, for monitoring and debugging automated information and measurement systems. A distinctive feature of the device is that it ensures the formation of a sequence of modifying realizations of the signal, represented in digital form, with rapidly varying waveform values in each implementation. The aim of the invention is to enhance the functionality by providing a variable duration and a variable period of pulses of the generated sequence. This goal is achieved through the introduction of block 5, the formation of time intervals, which contains counters 13, switch node 14, elements SHIII, 16, decoder 17. 1 3.p. f-ly, 2 ill. SL 00 co-ell 00 with Figure 2

Description

The invention relates to automation and computing and can be used to generate signals, presented in digital form, for monitoring and debugging automated information-measuring systems, systems for collecting and processing information in automated control systems.

The purpose of the invention is to expand the functionality by providing a variable duration and a variable period of pulses of the generated sequence.

Figure 1 shows the structural diagram of the proposed device; Fig. 2 is a block diagram of a block forming time intervals.

The device contains a counter 1, a memory block 2, a register 3, a counter 4, a block 5 forming time slots, a group of 6 outputs, a clock input 7, an output 8 of transferring counter 1, a reset input 9 of a block 5 forming a time intervals, a reset input 10 group II the outputs of counter 4, the counting input 12 of counter 4.

The time interval shaping unit 5 comprises counters 13, a switch node 14, elements OR 15 and 16, and a decoder 17.

The device works as follows.

The reset signal, received on the first input 10 of the reset, is set to the initial state of the counters 1 and 4, the counters 13 of the time interval forming unit 5. Memory unit 2 operates in a continuous sampling mode.

In block 2 of the memory, information about the waveform is stored in p memory zones for n different implementations. Counter 1 addresses a memory cell from p memory zones (i.e., forms the lower bits of the address of memory block 2), choosing a sequence of waveform values for one implementation. Counter 4 determines the memory zone (i.e., generates the high-order bits of the address of memory block 2), selecting one of the n signal implementations.

The time interval shaping unit sets a time interval during which the realization of the output signal does not change. After a predetermined interval, block 5 generates a pulse at its output 12

on which the second counter 4 is incremented. This leads to the choice of the next implementation of the signal in their sequence, etc.

From the memory cell addressed by the counter 1, the zone addressed by the counter 4 is read information. On the falling edge of the clock pulse, which enters the clock input 7 of the device, it is entered into register 3 and outputted into group 6 of the device outputs. At the same time, the counter 1 is incremented. Read out from block 2 of memory 5, information on the next clock pulse is entered into register 3 and outputted to group 6 of outputs. Thus, at the outputs of group 6, a sequence of signal values Q of signal (in digital form) is formed, corresponding to one realization of the signal.

. After all the cells of the memory area are scanned (counter 1 counts to the maximum), at the next 5 clock pulse at the clock output 7 of the device, the counter 1 at the transfer output generates a signal that is fed to the synchronous input 8 of the time interval shaping unit 5. 0 The state of counter 4 is fed to a group of 11 information inputs of block 5 of time intervals and a decoder 17. The signal at the output of the latter, corresponding to the code at its inputs, appears when there is a transfer signal at its building input and is fed to the counting input of the counter 13 corresponding to the selected implementation of the signal. The counters 0 in the initial state are reset by the signal arriving at their reset inputs on the reset input 9 of LOCK 5 through the OR element 15. The number of counters 13 corresponds to the number of 4g different signal realizations. According to Blinding 1m to the counting input of the pulses. The corresponding counter 13 is built up. By the node 14 of the switches, the output of the counter 13 is selected. Moreover, only one counter can be selected, i.e. the repetition may be 2,4,8, 16, ... times.

The signal from the output of the node 4 switches is given to the input of the element OR 16, the signal from the output of which resets the counter 13 (through the element OR 15), and is output to the output 12 of block 5 "With this signal is increasing

five

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the state of the counter 4, which leads to a change in the area of the memory block 2 and a change in the implementation of the output signal. In this case, the next counter 13 is selected by the decoder 17, which grows to the state specified by the switch node 14.

The output signal of the device is delayed by one clock cycle relative to the pulse sequence at the clock input 7. When the signal value in adjacent samples can be set arbitrarily within the limits determined by the bit size of memory block 2 and register 3, it allows forming a fast variable (in each sample) signal in each of its implementation.

Claims (2)

1. Device dp of forming digital sequences containing two counters, a memory block and a register, the group of outputs of the bits of the first counter connected to the first group of address inputs of the memory block, the outputs of which are connected to the information inputs of the register, the group of bits of which is a group of information outputs of the device, characterized in that, with the aim of extending the functionality by providing a variable duration and a variable period of pulses, , Introduced into the device forming unit time slots, wherein the clock input device is connected to the counters nym input of the first counter and WMOs the register recording resolution house, the reset input of the device is connected to the reset input of the first counter, the reset input of the second counter and the reset input of the time interval formation unit, the transfer output of the first counter is connected to the synchronous input of the time interval formation unit, the output of which is connected to the counting input of the second counter, the group of bit outputs of which is connected with the second group of address inputs of the memory block and with the group of information inputs of the block of formation of time intervals. 2. The device according to claim 1, characterized in that the block for forming time slots contains a decoder, two elements SH and n counters (where n is the number of outputs of the decoder), a node of switches, the synchronous input of the block forming time slots connected to the gate decoder input, the group the information inputs of which is a group of information inputs of the block, the outputs of the decoder from the first to the nth are connected respectively to the counting inputs of the counters, from the first to the nth inputs of the reset of which are combined and connected to the output the first OR element, the first input of which is the block reset input, the outputs of the bits of the counters are connected to the inputs of the switch node, the outputs of which are connected to the inputs of the second OR element, the output of which is connected to the second input of the first SHSh element and the output of the block. Editor I.Gorn Compiled by N.Toropova Tehred M. Khodanich Proofreader A, Obruchar 4222/38 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 1