SU1283771A1 - Logic analyzer - Google Patents

Abstract

The invention relates to the field of computing technology, namely to devices for monitoring and diagnostics of computers. The purpose of the invention is to expand the scope. The essence of the invention is that a known device comprising a clock, a register, a first, second, third counters, a memory block, a NOT element, an AND element and a delay element are additionally introduced a multiplexer, a frequency divider, a D-trigger, two element NAND, element AND, pulse shaper, element OR, and three delay elements. 4 il.

Description

one

The invention relates to computing technology, namely, computer monitoring and diagnostics devices.

The purpose of the invention is to expand the field of application by providing the possibility of analyzing information with an asynchronous period of arrival.

Figure 1 shows a block diagram of a device for logical analysis; FIG. 2 is a time chart of reading information accumulated in the device; FIG. FIG. 3 is a time diagram of the operation of the device in the collection mode; Fig. 4 shows a format for presenting information in a memory unit.

The device contains a generator of 1 clock pulses, register 2 shift, counters 3-5, switch 6,

memory block 7, AND-NE elements 8 and 9, AND elements 10 and 11, frequency divider 12, element OR 13, element IPI-NOT 14, D-flip-flop 15, element. NOT 16, delay elements 17-20, input 2 i set the operation mode, information input 22, start input 23, address inputs 24 and device outputs 25.

The device works as follows.

Depending on the value of the operation mode signal at input 21, two modes of operation of the device are distinguished:

- collection of information coming from the object;

-analysis of accumulated information. Transition signal operation mode

input 21 from state 0 to state 1 means the device collects information. The device operates in the mode of collecting incoming information from the input 22 through the register 2 of the information shift and its memorization in the memory block 7 until the moment of overflow

20

25

thirty

35

40

The form for filling the memory block 7 with information received from the input 12 of the device is shown in FIG. 4. When writing information in the U format, two options are possible: counter 3 is filled in all bits O and 1 These two options differ from each other in that (1 + 1) and bit of memory block 7 (1 is the length of the array analyzed information) is indicated by the presence of O and, i.e. sign of a constant. The presence of a low level at one of the inputs of the NAND element 8 maintains a high level at the D-input of D-flip-flop 15, which, on the front of the signal from the output of dividers 12 frequencies through delay element 17, sets the flip-flop 15 in 1 trigger 15 is written to the (1 + 2) th bit of memory block 7. Signal 1 at output B of trigger 15 blocks the passage of a strobe signal through the OR element 13 and switches switch 6 to the switching state of counter 4 for information inputs of memory block 7. Element OR - NOT 14 with dynamic inputs removes the appearance of a signal edge,. a transition from state 1 to state O on any of its inputs and forms a low level signal which

4 zeroes counter 4 and through the element and until the signal is turned off

Nala mode of operation. The presence of an overflow signal from the inverse output of the counter 5 and O at the input 21 blocks the operation of the generator 1 clock

pulses through element 11. I

The operation of the device in the mode of collecting information from the object is explained in the time diagram of FIG. 3. After starting, the clock pulse generator 1 generates a clock signal that shifts the incoming input information in register 2 and is the input signal 50

55

enters the clocking input counter 5 and adds one. Element ШШ-НЕ 14 excludes writing to the memory block at the same address when collecting information on 4 hermat. About different values of the constants in each assembled cycle. When collecting a signal of the type constant or constant 1, the value of the counter 5 remains unchanged, and the value of the counter 40, which counts the number of ticks of the presence of the constant, changes with s. Thus, information from the output of counter 4 is recorded in one

2

scrap for divider 12 frequency. The information accumulated in shift register 2 is rewritten into counter 3 by the front of a signal from frequency divider 12. Depending on the information copied to the first counter, there are two recording formats (reset) of information:

-format O G constants- type O

type 1 constants

-format 1 mixed information.

The form for filling the memory block 7 with information coming from the input of the device is shown in FIG. 4. When writing information in the U format, two options are possible: counter 3 is filled for all bits O and 1. These two options differ from each other in that (1 + 1) and bit of memory block 7 (1 is the length of the array of the analyzed information) is indicated by the sign of the presence of O and, i.e. sign of a constant. The presence of a low level on one of the inputs of the NAND element 8 maintains a high level on the D-input of D-flip-flop 15, which, on the front of the signal from the output of 12 frequencies through the delay element 17, places a flip-flop 15 in 1. The value of the signal from the D-flip-flop 15 is recorded in the (1 + 2) -th bit of memory block 7. Signal 1 at output B of trigger 15 blocks the passage of a strobe signal through the element OR 13 and switches switch 6 to the switching state of the outputs of counter 4 to the information inputs of memory block 7 . Element OR-NOT 14 with dynamic inputs monitors the appearance of a signal,. . , transition from state 1 to state O on any of its inputs and forms a low level signal, which

reset counter 4 and through element mt, o

enters the clock input of the counter 5 and adds one. Element ШШ-НЕ 14 excludes writing to the memory block at the same address when collecting information on 4 hermat. About the different values of the constants in each assembled cycle. With a long-term collection of a signal of the type O constant or constant 1, the value of counter 5 remains unchanged, and the value of counter 40, counting the number of ticks of the constant, changes. Thus, information from the output of counter 4 is recorded in one

3

and-: mku of block 7 years until the NA overflows this counter 4, the signal from the overflow output of which adds 1 to the value of counter 5, receiving the new address of the next cell of memory 7. Record input of the memory block in mode collection of incoming information found 0

dits in the state

record entry

which, according to the timing diagram of FIG. 3, processes the recording procedure. The inverted delay element 19 requires a dp compensation for the response time of the elements AND-HE 9, counter 5, and the W-NOT element with dynamic inputs.

When recording the information coming from the object in format 1 into counter 3, the mixed information is rewritten. As a result, signals 1 are present at the outputs of counter -3. Thus, the D-trigger with the first clock signal is set to O, the signal from KiDTOporo switches switch 6 to the translation of information from the outputs of counter 3 to the information group of inputs of memory 7, according to the information the input of which is written O is a sign of format 1. The signal O at the input of the element OR 13 permits the passage of the signal to the input of the element NAND 9, from the output of which the signal goes to the input of the count of 5, which adds one to the current address, etc. The delay elements 17 and the elements 18 and 19 of the delay with inversion are necessary dp stable error-free operation of the device in the mode of collecting information from the object of diagnosis. When a signal O arrives at input 21, the device enters the analysis mode of information accumulated in memory block 7. Read and analyze. The accumulated information is carried out according to the timing diagram shown in FIG.

The formation of information recorded in memory 7 makes it possible to analyze large arrays of incoming information without reducing its scanning frequency14.

Claims (1)

Invention Formula A logic analyzer containing a clock pulse generator, a shift register, three counters, a memory block, an item NOT, a first AND element, 8377I4  element delay, where the first element of the delay element is connected to the first input of the first element I, the output of the clock generator .c pulses connected to the synchronous input of the shift register, whose information input is the information input of the analyzer, the group of outputs of the register is connected to the group of information inputs. the first counter, the analyzer's address inputs are connected to the information inputs of the second counter, the group of bit outputs of which is connected to the address) group of inputs of the memory block, the outputs of which are The outputs of the analyzer, the mode setting input of which is connected through the element NOT to the recording input of the memory unit, the synchronization input 20 of which is connected to the output of the first element I, the start input of the analyzer is connected to the recording input of the second counter and the input of the first delay element differing - 25 s so that, in order to expand the scope by providing information analysis with an asynchronous arrival period, the analyzer contains a switch, a frequency divider, a D-trigger, two AND-NOT elements, a second AND element, an OR-H element E, OR element, second, third and fourth delay elements, with the output of the 35-pulse generator connected to the input of a frequency divider, the output of which is connected to the recording input of the first counter and through the second delay element to the D-trigger synchronous input of the third counter and the inputs of the third and fourth delay elements, the inverse outputs of which are connected to the first input of the OR element and the second input of the first element AND, the output of the D-flip-flop is connected to the control input of the switch, the second input. the house of the OR element and the information input of the memory unit, the information inputs of which are connected to the switch 0, the first group of information inputs of which are connected to the bit group of the X outputs of the first counter, the second group of information inputs of the switch are connected to the 5 bit outputs of the third counter and the senior output the discharge of the first counter, the input of the record of the first counter is connected to the input of the task of the analyzer operating mode, inverse 1 The output of the transfer is Greek. About the counter is connected to the first input of the first NAND element, the second input of which is connected to the output of the OR-NOT element, to the inverse reset input of the third counter, the overflow output of the second counter is connected to the second input of the second And element whose output is connected with a clock pulse start input; an inverse overflow output; go (. connected to the first AND of the second AND-NOT element and the OR-NOT element; the inverse output of the HERV meter counter is connected to the second inputs of the second AND-NOT element and the OR-NOT element; the output of the OR element is connected to the third the input of the NAND nerve element, the output of which is connected to the synchronous input of the first counter, the output of the second element of the NAND connected to the D-INPUT of the D-flip-flop. B) one 2 5 (7 Infor 1ai F1A2 Inspiration Dospuvern 3anyci PP Frequency splitter output Second exercise CT25 The second control, LB. 7 HHqj- Inputs dl. 7 opMQm Value of the Vt / c / io const clock cycles during the FD Constants Signal Value at 1 FIG. - Ying (rormai, and reliable Phie, 3