SU1265778A1 - Multichannel device for test checking of logic units - Google Patents

Abstract

The invention relates to automation and computing and can be used in test control equipment and tuning of logical nodes and blocks. The purpose of the “invention is to increase the reliability of the control. The device contains accumulated :; test unit, control unit, decoder, control channels, each of which includes a switching register, data register, switch, reference element, address counter, comparison unit, OR element, delay element, time divider, time label register. The device allows the node to be monitored in accordance with the working sequence of the timing patterns of its actual operation. First, the test accumulator receives data on the location of the inputs and outputs of the monitored address, while the switching registers are opened, then the same outputs are on (L turn off the signals of the monitored node, test words and reference responses. Time of control is recorded in the time divider. 4 Il.

Description

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00 The invention relates to automation and computing and can be used in the equipment of test control and adjustment of logical nodes and blocks. The purpose of the invention is to increase the reliability of the control. Figure 1 shows the structural diagram of the device; Fig. 2 is a control block diagram; in FIG. 3, the block diagram of the time divider; 4 is a time diagram of the operation of the device. The device contains 1 test drive with address decoder 2, address counter 3, monitored logic node 4, control block 5, time divider 6, time register 7 timestamp, comparison block 8, n control channels 9, each of which contains a data register 10, switching register 11, switch 12, comparison element 13, as well as decoder 14, OR element 15 and delay element 16 Control unit 5 (FIG. 2) contains a trigger 17, pulse former 18-20, elements OR 21-23 and delay element 24 . The time divider 6 (FIG. 3) comprises a time pulse generator 25, a time divider 26, and a time counter 27. The device works as follows. In the initial state, the 3-address counter, the timestamp register 7, the time divider 6, the trigger 17 of the control unit 5, the data register 10 and the switching register 11 are set to the zero state. When the switch is started, the driver 18 generates a single pulse (figure 4, B), which through the element OR 22 from the first output of control unit 5 (figure 1 and 2) through the element. OR 15 enters the input of the delay element 16 and Synchronization input of decoder 2 addresses of the accumulator of 1 tests. Since the trigger 17 is in the zero state, from the fourth output of the control block 5 enters the resolving potential, which opens the switching register 11 (Fig.A, F). Therefore, the information read from the 0th memory location is transferred to the switching register 11. The same single pulse delayed by the delay element 24 from the second 78 output of the control unit 5 is fed to the input of the record of the register 7 of time stamps and the input of the synchronization of the register 10 of data. Since at the time the resolution register of the data register 10 is present, the inhibitory potential from the direct output of trigger 17 is present, the data register 10 is not received, and the time register register 7 receives information about the discreteness of the time stamps when testing this logical node. Thus, the first pulse enters into the register 7 the division ratio for time stamps of the time generator 25, as well as information on the inputs and outputs of the checked logical node 4 to the switching register 11. The input contacts of the checked logical node 4 are connected via the switch 12 to the data register 10, and the output contacts of the control object 4 are connected to the comparison element 13. In addition, the address counter 3 is set to the state of one, and the division factor 26 is entered into the division factor (time stamp resolution). The positive front of the first single pulse, arriving at the input of the pulse generator 19, generates a second single pulse (FIG. 4, c), which sets the trigger 17 in one state, starts the time generator 25 and reads the information from 00 ... 01 cell of the memory in which the time of the label of the next test word and the test set of the installation in the initial state of the logical node 4 are stored. This test set is necessary for logical nodes that contain memory elements, i.e. built on sequential circuits. Since the trigger 17 is set to one, the test word for the installation of the logical node 4 being checked enters the data register 10 (FIG. 4, E) and sets the control object 4 to the initial state. At the same time, the register 7 receives the time stamp of the occurrence of the next test word, which from the register 7 outputs goes to the matching inputs of the comparison block 8. Reading of this word occurs only at the moment of coincidence of the current value of the time stamp.

time generated in the counter 27, with the value of the time stamp located in the time stamp register 7. The second single impulse delayed by delay element 6 sets the address counter 3 to 00 ... 10 i.e. prepares the reading of the contents of the 000 ... 10th memory location.

When the current time coincides with the timestamp of the next test word, a pulse appears at the output of the comparison unit 8 (FIG. 4, K), which, entering the shaper 20 of the control unit 5, generates a pulse (FIG. 4, A), which The first and second outputs of the control unit 5 are fed to the address decoder 2 (FIG. 4, I), to the address counter 3 (FIG. 4.3) and to the synchronization inputs of the data register 10. When this happens, the test word from the memory cell 000 ... 10 is read into the register 7 timestamps and the data register 10, the counter 3 addresses with a certain delay (Fig.4.3) takes the value 000 ... 11, to the input contacts of the monitored logical node 4 is fed through switches 12, the input actions, the instantaneous output reactions of the monitored logical node 4 are compared on the comparison element 13 with their reference values which are recorded in the data register 10.- Since the instantaneous response of the monitored logical node does not appear all If the outputs are dependent on the internal structure of the logical node, then at other outputs the reactions may appear in the time interval corresponding to the second, third, and so on test words. Therefore, the test words recorded in the second memory area of the test accumulator have in the first memory area the corresponding timestamp by which the test influences are read and supplied and the reference output reactions in strict accordance with the timeline of the specific logical node 4. In the first the memory areas of the test field are the time stamps of the (i + l) -ro test word, i.e. at the stage of control of the logical node 4 on the i-th test word, the register of 7 timestamps already contains the (1 + 1) -th timestamp.

If the output reaction of the controlled logical node 4 does not coincide with its reference value on the data register 10, the corresponding comparison element 13 generates a potential that enters the first input of the control unit 5 and converts the trigger 17 to the zero state, which bans the formation of subsequent time stamps divider 6 times.

When the output reactions of the controlled logical node 4 coincide with their reference values, the time divider 6 does not stop and accumulates the values of the time intervals in the counter 27 until its value coincides with the time stamp stored in register 7.

Further verification is carried out in the same way.

The size of the first test drive area 1 is determined by the ratio

N,

where Q is the total number of tests for the logical node control;

1 - bit, which determines the information belonging to the test word;

2 is the bit of a time division division mark;

3-bit, indicating the control completion code.

The size of the second region of the accumulator 1 test is determined by the number of inputs and outputs of the controlled logical nodes.

When the termination control code is decoded by the decoder 14, a signal is generated, which enters the control unit 5 and stops the operation of the device.

The outputs of the element in 13 comparisons can be displayed, the lack of indication means that the control unit 4 is healthy.

In the case of the coincidence of the output reactions of the controlled logical node 4 with their reference values, the device is stopped, and according to the state of the comparison elements 13 it is possible to judge the number of the mismatched output contact.

The device allows the logical node to be monitored in strict accordance with the working sequence of the time cyclograms of its real operation. of the invention Multi-channel device of the test control of logical nodes, containing the test drive, control unit, decoder, and n control channels (where n is the number of inputs and outputs of the controlled logical node), each of which contains a switching register, data register,. a switch, a comparison element, and in each iM control channel (, ..., p), the output of the reference data register response is connected to the first information input of the comparison element, the test action output of the data register is connected to information the input of the switch, the control input of which is connected to the output of the switching register, the output of which is connected to the second information input of the comparison element and the corresponding input-output of the monitored digital node, while the outputs of the comparison elements all the control channels are device output signals different from that, in order to increase the control accuracy, the device contains an address counter, a comparison block, an OR element, a delay element, a time divider, a time stamp register, and a control block with It has three pulse drivers, a delay element, a start switch, three OR elements and a trigger, and the input of the first driver of the im-: pulses is connected to the unit potential potential bus of the device through the start switch, the output of the first pulse generator OR is connected to the first input of the first element OR the control unit and through the second pulse generator with the first input of the second element OR of the control unit 8, with a single input of the trigger, the start input of the time divider and the first input of the OR element, the second input of which one with the output of the first OR element of the control unit and with the second input of the second OR element of the control unit, the output of which is connected to the synchronization inputs of the data registers of all control channels and the record input of the time stamp register through the delay element of the control unit; the input of the third OR element of the control unit, the second and third inputs of which are connected to the device reset input and the output of the decoder, whose information inputs are connected to the outputs p The time stamp register with the first group of inputs of the comparison unit and with the information inputs of the time divider, the outputs of which are connected to the second group of inputs of the comparison unit, the output of which is connected through the third pulse shaper to the second input of the first OR element of the control unit, the output of the third OR element of the control unit is connected with the zero input of the trigger, the direct output of which is connected to the enable inputs of the data registers of all control channels, the inverse output of the trigger is connected to the inputs of the resolution of the register registers tions of all control lanes, information inputs of all data registers and switching registers of all control channels are connected to the test information outputs of the test accumulator, the outputs of which are connected to the information inputs of the time stamp register, the output of the OR storage element and through the delay element with the counting input of the address counter, the outputs of which are connected to the address inputs of the test accumulator.

Match

FIG. 2

From register 1

Claims (1)

Claim • A multichannel device for test control of logical nodes, containing a test drive, a control unit, a decoder, and η control channels (where η is the number of inputs and outputs of the controlled logical node), each of which contains a switching register, data register, switch, and a comparison element, and each ί-th control channel (ί = Ι ,,, η), the output of the reference response of the data register is connected to the first information input of the comparison element, the output of the test effect of the data register is connected to the information input of the switch, The incoming input of which is connected to the output of the switching register, the output of which is connected to the second information input of the comparison element and the corresponding input-output of the monitored digital node, while the outputs of the comparison elements of all control channels are outputs of the device error indicator, characterized in that, in order to increase the reliability control device contains an address counter, a comparison unit, an OR element, a delay element, a time divider, a register of time stamps, and the control unit contains three shapers pulses, delay element, start switch, three OR elements and a trigger, and the input of the first pulse shaper through the start switch is connected to the unit potential bus, the output of the first pulse shaper is connected to the first input of the first OR element of the control unit and through the second pulse shaper with the first input second element OR control unit with a single input.trigger, the start input of the time divider and the first input of the OR element, the second input of which is connected to the output of the first 5 OR element of the control unit and with the second input of the second OR element of the control unit, the output of which is connected to the delay element of the control unit the synchronization inputs of 10 data registers of all control channels and the input of the register of timestamps, the outputs of the comparison elements of all control channels are connected to the first input of the third element OR 15 of the control unit, the second and third inputs of the cat They are connected to the reset input of the device and the output of the decoder, the information inputs of which are connected to the outputs of the timestamp register 20, to the first group of inputs of the comparison unit and to the information inputs of the time divider, the outputs of which are connected to the second group of inputs of the comparison unit, the output of which 25 is connected through the third a pulse shaper with a second input of the first OR element of the control unit, the output of the third OR element of the control unit is connected to the zero input of trigger 30 ger, the direct output of which is connected to the inputs of permissions of the data registers of all control channels, the inverse trigger output is connected to the enable inputs of the switching registers of all 35 control channels, the information inputs of all data registers and switching registers of all control channels are connected to the outputs of the test information of the test drive, the outputs of which 4Q time field is connected to the information inputs the timestamp register, the output of the OR element is connected to the synchronization input of the test drive and through the delay element45 with the counting input of the address counter, the outputs of which oedineny to an address input test drive. ΛοΙ mDymk What word 4 „ itka / rgyaa Test word 4-) • • ·. HUHulntKlZj Test word! Installation! Tmt comem tB0.8en.8p. Komeotai »vgoOev-vshovoO W 8 X _________ FIG. G From register 7 t Lt. _τ ί l \ _ t ' \ g * and ™. # h \ 3 Utn. ( ¹ . π p I g * ""TO I / ' T1 / Um.H pp P / and _so on pp 1 T ^f Um.E 11 _r t Figure 4