SU1013960A1 - Two-processor system checking device - Google Patents

Abstract

A DEVICE FOR CONTROL OF DIGITAL KNOTES, containing a memory unit, a comparison unit, a control unit, a test information generation unit, a test register, a multiplexer unit, a switch; wherein the first output of the control unit is connected to. the first control input of the test information generating unit; the second control input. which is connected to the second output of the control unit, the third output of which is connected to the control input of the two unit, the output group of which is connected to the group of information outputs of the test information generation unit, the group of information outputs of which is connected to the group of information inputs of the test register that controls the input of which is connected to the control output of the test information generating unit, the output of the memory unit is connected to the first input. the house of the comparison unit, the output of which is connected to the input of the control unit, the fourth and fifth outputs of which are connected respectively to the clock and counting inputs of the multiplexer unit, so that with the purpose of controlling the device, the switch contains a group of limiting resistors, a group of key transistors, the bases of which are connected to the register of the test, respectively, the emitters of key i transistors are connected to the bus of the zero potential of the switch, the collectors of the key transistors of the switch connect Nena with inputs limiter resistors, to the outputs of checks in direct assembly with the block information multiplexer inputs ,, the output of which is connected to the second input of the comparing unit, the output restriction, the switch resistors are connected to the power supply line switch. co f

Description

The invention relates to computing and can be used to monitor and diagnose logical blocks and digital computer nodes. A device for testing logical blocks is known, which contains an input block, a control block, an output switch, a controlled block, a random number generator, a random number converter. , - display unit and static analyzer unit fl}. However, such a device is complicated because the inputs of the controlled logic block are connected to the outputs of the case converter, and the outputs of this block are connected to the inputs of the switch. This requires additional switching means that separate the inputs and outputs individually for each block. The closest in technical solution to the present invention is a multichannel test device for controlling digital computer nodes, which contains a storage unit for storing tests, a test register, input and signal drivers, a switching unit, a comparison unit and an object of control, and the memory cell of any of the bits the test register is connected via an output driver and a switching device switch, and through a parallel circuit connected to them and the input driver to the input contact are checked Digital node 2.: However, the known device is a long-range device due to the large number of switches, input and output signal drivers, the purpose of the invention is to simplify the device, the goal is achieved by the fact that the device for controlling digital nodes containing a memory unit, a comparison unit, a control unit, a test information generating unit, a test register, a multiplexer unit, a switch, wherein the first output of the control unit is connected to the first control input of the test information generating unit. The second control input of which is connected to the second output of the control unit, the third output of which is connected to the control input of the memory block, the output group of which is connected to the group of information inputs of the test information generation unit, the group of information outputs of which is connected to the group of informational outputs of the test register, the control in. The path of which is connected to the control output of the test information generating unit, the output of the memory block is connected to the first input of the comparator block, the output of which is n the input of the control unit, the fourth and fifth outputs of which are connected respectively to the clock and counting inputs of the multiplexer unit, the switch contains a group of limiting resistors, a group of key transistors, the bases of which are connected respectively to the outputs of the test, the emitters of the key transistors are connected to the zero potential bus the switch, the collectors of the key transistors of the switch are connected to the inputs of the limiting resistors, to the outputs of the tested node, to the information, to the inputs of the block ipleksora whose output is connected to a second input of the comparison unit outputs the switch limiting resistors connected to the power supply bus. switch,. Fig. 1 is a functional block diagram of the device; Fig. 2 is a functional block diagram of the control unit. The device consists of a memory block 1, a test information generation unit 2 including shapers 3, a write counter 4 and a decoder 5 write gates, a test b reg register, a switch 7 consisting of a group of key transistors 8, a group of limiting resistors 9 and a reference N. Paragraph 10, digital. node 11, multiplexer unit 12, representing an f-bit N-input multiplexer 13 with address selection, controlled by counter 14, comparator unit 15 and control unit 16. The control unit 16 consists of a pulse clock generator 17, a start switch 18, a single pulse generator 19, an AND two-input element, a start trigger 21, a three-input AND 22 input, a recording 23 trigger, a two-input element OR .24, a counter of 25 recording cycles, a two-input the element And 26, the counter 27 read cycles, the two-input element And 28, the counter 29 of the address, the trigger 30 error, the three-input element And 31, the indicator 32 errors. The device works as follows,. . The test information from memory block 1 through the test information generation block 2 is sequentially recorded in K words using k bits into the test register B using recording gates, which are selected by the record count 4 and formed by the write decoder 5 under the action of the control and pulse from the output of the element 26 control block 16. On the falling edge of this strobe, counter 4 changes its state, selecting the next recording strobe. . - Register b test consists of P separate registers. Each of these registers has k information bits and one recording gate. The formers 3 of the test information generating unit 2 are designed to provide load capacity along the inputs of the test register 6. Writing information to the test register is done P times. The test information, which is recorded in the Test register B, represents the set of input effects and masks. All bits of the register b, which correspond to the inputs of the tested node 11, are recorded for input effects, and for all bits, KOTOjMjie correspond to the outputs of the test object, masks are simultaneously recorded. The values of the masks, which correspond to the outputs of the tested node 11 and are recorded on the test register B, must be so that the elements with an open collector 8 of the corresponding bits of the switch 7 are closed. In this case, the elements with an open collector will not load the outputs of the tested node 11. The load for THESE outputs will only be high limiting resistors 9. The values of the input effects on the test test register when issuing the next Test effects change, and the key transistors 8 of the switch 7, which are uzhdayuts these input exposure E, in one case can be opened and closed in a second, unlike masks that when vvdache next test influences acting elements are verified and hold 8-closed state. IF the open collector elements are open, then each of these inputs of the tested node will have a zero potential, and if they are closed, then the potential of the reference voltage. In the first case, the input currents of the tested node will be determined by the key transistors and in the second in this case, the values of the limiting resistors 9 and the source 10 of the reference voltage. If logic is used as an object of control, for example), on TTL elements, tO to provide a logical unit on standard inputs, a current is required that is measured in tens of microamperes, and to provide a logic zero, in milliamperes. If the limiting resistor has a nominal value that provides a logical unit for the input (a logical zero provides a key transistor, then the load for the outputs of the node being tested will only be these limiting resistors that will not be reflected on the output's operability (less than one OUT load) Under the action of input effects at the outputs of the tested node, reactions appear. Since for all outputs the key transistors are closed and the limiting resistors do not prevent the appearance of output reactions , the input actions and output reactions of the tested node arrive at block 12. Since the block .12 is an f-bit N-input multiplexer with address selection, controlled by the counter 14, information N in words on f bits is output sequentially at block 15 and compared with the expected information that arrives at the comparison unit from block 1, Counter 14 changes its state according to the counting pulse, which is generated by element 28 of control unit 16. Initially, counters 4 and 14 are set by the signal KOTOZH1Y produces With the generator 19 single pulses of the control unit 16, the test information, which is outputted to the test register 6, may be different from the expected one, i.e. k may differ from f. This will not reflect on the performance of this device. In this part of the bits of the memory block may not be used. The control unit 16 operates barely: in the following manner, the clock pulse generator 17 continuously B191 operates. This: cc impulses. The clock pulse of the first output is out of phase with respect to the clock pulse of the second output so that they do not overlap with each other. These pulses provide synchronization of the entire device. When you press the start button 18 on the clock pulse of the first output, the generator 19 of a single pulse produces a trigger pulse. By this impulse, trigger 21 and trigger 23 are set to one state, and error trigger 30 and counters 25, 27 to 29 are set to zero, counters 4 and 14 are also cast to zero state,. both by the first input, by the single value of the trigger 21, and by the clock pulses of the second output 17 of the output element of the element 20, pulses are generated.

In the initial state, the trigger 23 of the record is in the unit. At the output of the element 26, the unit value of the trigger 23 and the pulses from the output of the element 20 produce recording pulses, which enter the counters 25 and 4 and the gate input of the decoder 5 4 For each pulse c the output of element 20, at one of the outputs of the decoder 5, which is selected by the counter 4, a strobe appears, on which ipoMy the input is recorded. , impacts and masks from the storage unit 1 to the register 6 of the test. On the falling edge of this pulse from the output of element 20, t, e, after recording the next information from memory block 1 to test register 6, the contents of counter 29 are incremented by one. This means that the next word is selected from memory block 1. Counter 4 also changes its contents by selecting the next recording gate. Counter 25 monitors the number of words recorded from memory block 1 in test register 6. Upon completion of the last word recording, the counter 25 generates an overflow pulse, which, through the input of the OR element, enters the counting input of the trigger 23 and switches it to the zero state. Further recording of information in the test register does not occur, since element 26 is disabled in this case. When the trigger goes into the zero state, on the lane. The first input of element 28 and the third input of element 31 is a resolving potential,

When issuing the next pulse from the output of the element 20 according to the zero state of the first trigger 23, the element 31 analyzes the error that comes from the Comparison circuit 15 to its second input. If an error occurs, then a pulse appears at the output of this element, which sets the trigger 30 for an error on the second move in a single step, giving information to the 32 error indicator. In addition, a permitting potential appears at the third input of element 22. If the error at the second input of element 31 is absent, then the trigger from the signal remains in the zero state. This occurs when information from memory 1 is located at the address that is located in counter 29 and enters memory 1. Compared with information

which comes from the checking node 11 through one of the directions of the multiplexer 13 defined by the counter 14,

5 On the trailing edge of this pulse from the output of element 20, the contents of each of the counters 14, 27 and 29 increase-. chivae.ts per unit. This means that the next word for comparison will be received from memory block 1, and multiplexer 13 will connect the next group of inputs and outputs of the control object. Counter 27 counts the number of compared words

5 At the end of the analysis of all contacts of the control object, the counter 27 issues an overflow signal, through which the OR trigger element 24 changes the state of the trigger 23

0 at the counting input per unit. Again, registering the test 6 of the next action P with the words of k bits, is written again, and the cycle repeats. When an error is detected after peg triggering of the trigger 23 into a single state, a clock pulse of the first output of the generator 17 is outputted, the output of the element 22 produces a pulse, according to which the trigger 21 of the start goes into the zero state and the device stops with an error indication on the indicator 32,

The use of this device will make it possible to reduce hardware costs with a large number of checked points, as well as expand its area of application, for example, for the continuity of boards and harnesses, where there are a large number of control points.

Fig. /

Claims (1)

DEVICE FOR MONITORING DIGITAL ASSEMBLIES, comprising a memory unit, a comparison unit, a control unit, a unit for generating test information, a test register, a unit of multiplexers, a switch; moreover, the first output of the control unit is connected to · the first control input of the test information generation unit, the second control input of which is connected to the second output of the control unit, the third output of which is connected to the control input of the memory unit, the output group of which is connected ·? · yen with the group of information outputs unit for generating test information, the group of information outputs of which is connected to the group \ information inputs of the test register, the control input of which is connected to the control output of the unit · Test information, the output of the memory unit is connected to the first input of the comparison unit, the output of which is connected to the input of the control unit / the fourth and fifth outputs of which are connected to the clock and counting inputs of the multiplexer unit, respectively with the fact that, in order to simplify the device, the switch contains a group of limiting resistors, a group of key transistors, the bases of which are connected respectively to the outputs of the test register, the emitters of the key transistors are connected to the zero potential bus utator, collectors of key transistors of the switch are connected to the inputs of the limiter resistors, with the outputs of the tested node, with the information inputs of the multiplexer unit. the output of which is connected to the second input of the comparison unit, the output of the limiting resistors of the switch is connected to the power bus of the switch. 1013960.