SU1647435A1 - Voltage extremum meter - Google Patents

Abstract

The invention relates to the computation of vt (t) and information and measuring equipment and can be used in the processing of information from the sensors of automated test systems. The purpose of the invention is to expand the functionality by providing a multi-channel interrogation of the sources of measured signals and determining the minimum and maximum for each channel. The purpose of the invention is achieved by using an analog switch 3, a storage device 10, a digital comparator 11 and the corresponding connections between blocks. The device also contains a generator 1, blocks AND 2.15, analog-to-digital converter 4, inverter 5, elements AND-NOT 6, 9, 14. address counter 7, triggers 8, 13. 17, distributor 12 pulses. 1 il.

Description

The invention relates to computer technology and can be used in the processing of information coming from process sensors or automated test systems, where it becomes necessary to determine the maximum and minimum signal values.

The purpose of the invention is the expansion of functionality by providing a consistent survey of the sources of the measured signals and at the same time determining the maximum and minimum for each channel in real time.

The drawing shows a block diagram of a meter.

The meter contains a clock generator 1, a first element And 2, an analog switch 3, an analog-to-digital converter 4, an inverter 5, a first element AND-NOT 6, an address counter 7, RS-trigger 8, a second element AND-NOT 9, a storage element 10, a digital comparator 11, a pulse distributor 12, a first D-trigger 13, a third AND-NOT element 14, a second AND element 15, an OR element 16, a second D trigger 17.

The output of the clock generator 1 is connected to the first input of the first element And 2, the second input of which is connected to the second input of the meter. The output of the first element And 2 is connected to the first input of the pulse distributor 12, the first output of which 18 is connected to the first synchronizing input of the analog-to-digital converter 4. The second input of the last is connected to the output of the analog switch 3, the inputs of which are connected to the input terminals of the meter for connecting the sources of the measured signal and the address inputs with the address inputs of the memory element 10 and the information outputs of the address counter 7. The second output of the address counter 7 is connected to the second input of the second element INE-coagulant 9, the first input of which is connected to the high bit _r A first information input group of digital comparator 11 and the direct output RS-flip-flop 8, R-input of which is connected to the third output of the address counter 7. R-input of the address counter 7 is connected to S - RS trigger input 8. with the second input of the pulse distributor 12 and the third input of the meter Reset, and the C-input of the address counter is connected to the output of the first AND-NOT 6 element, the second input of which is connected to the first input of the meter, and the first input through the inverter 5 - with the second output distribution of Tell 12 pulses. The third output 20 of the latter is connected to the C-input of the first D-flip-flop 13, and the D-input of the first flip-flop 13 is connected to the first input of the OR element 16 and the output of Less digital comparator 11. The senior bit of the first information group of the digital comparator 11 is connected to the logical Ό bus. An output More than a digital comparator is connected to the second input of the second AND element 15, the first input of which is connected to the inverse output of the first D-trigger 13 and the second input of the third INE element 14. The first input of the AND-14 element is connected to the output of the second AND-NOT 9 element, and the output is with the (n + 1) -th bit of the address input of the storage element 10, the recording input of which is connected to the inverse output of the second D-trigger 17. The D-path of the trigger 17 is connected to the output of the OR element 16, the second input of which is connected to the output of the second element And 15. R-input of the first D-trigger 13 under for prison to the fourth output 21 of the distributor 12 pulses, a fifth output 22 coupled to an S-input and six outputs 23 - with R-input of the second D-flip-flop 17,

In the operation of the meter, two main modes can be distinguished: registration of extrema for each measuring channel and reading of the found values into a device that ensures their further processing. The meter can be controlled, for example, from a microcomputer, with the help of which control signals are generated Sampling or reading (Select / read), Clock pulses (TI), Reset. The microcomputer provides further processing of the obtained extrema, for example, the calculation of the span for each channel.

In addition, the meter has an auxiliary mode - initial recording, performed once before the extremes recording mode and allowing to write the initial values of the codes of the measured signals into the memory element 10, which eliminates the possible occurrence of codes in the memory that exceed the range of the measured signals.

In the initial recording mode, at the second input of the meter, the signal “Select / Count” is set, which corresponds to the level of logic 0. At the first input - TI, which corresponds to the level of logical 1. At the input Reset of the meter, a single pulse is generated, which resets address counter 7 to 0, at the direct output The RS-flip-flop 8 sets the logic level 1, and also sets the pulse distributor 12 to the initial position. In this case, pulses are formed at the fourth 21 and sixth 23 outputs of the pulse distributor, resetting the first 13 and second 17 D-flip-flops. The signal from the direct output of the RS-flip-flop 8, arriving at the senior bit At the first information group of the inputs of the digital comparator 11, at its output sets the logical level 1 more regardless of the ratio of the codes at the outputs of the analog-to-digital converter 4 and the storage element

10. After completion of the “Reset” pulse and applying to the input Select / read logic 1 level in the meter, a sequential review of the measured signal sources begins.

The pulses from the generator 1 clock pulses through the open first element And 2 are fed to the first input of the distributor 12 pulses. According to the synchronizing pulse from the first output of the pulse distributor, the analog-to-digital converter 4 generates a code of the measured signal through the measuring channel, the number of which is determined by the address counter 7. The address of the measuring channel and memory cell of the memory element 10 is changed by the signal from the second output 19 of the pulse distributor passing through the inverter 5, the first I-NB element 6 to the counting input of the address counter 7. The first D-trigger 13 remains in its original position, since the logical level is maintained at its D-input about 0 ". A single signal from the output is greater than the digital comparator 11, passing through the second element And 15 and the element OR 16. is fed to the D-input of the second D trigger 17. On the synchronizing pulse from the output 22 of the distributor 12 pulses, the signal from the inverse output of the D trigger 17 generates a recording signal, according to which data from the outputs of the analog-to-digital Converter 4 are recorded in the storage element 10. The pulses from the fourth 21 and sixth 23 outputs of the distributor 12 pulses are reset first 13 and second 17 D-flip-flops. The process is repeated until the data codes of all M measuring channels are stored in the memory in the memory area intended for storing maxima (the number M is chosen so that M = 2 ^P. where η is an integer).

After filling in the entire area in which the maxima are stored, a logical 1 ”appears in the (l + 1) -th digit of the address counter 7. This signal passes through the second AND-NOT element 9 and the third AND-NOT element 14 and. arriving at the (n - »- 1) th address bit of the memorizing element 10, it begins to address the memory area intended for storing the minima of the measured signals. After filling this area in the (n + 2) m category of the address counter 7, a logical 1 ”appears, which resets the RS-trigger 8. The zero level at the direct output of the RS-trigger 8 supports the output of the second AND-NOT 9 element, the logic level 1 regardless output status (n + 1) -th category of the address counter 7. In addition. The RS-flip-flop 8 sets logic 0 at the input А _{t of the} digital comparator 11, allows the comparison of the codes of the analog-to-digital comparator 11 and the storage element 10, i.e. the meter goes directly to the extremes registration mode.

In the registration mode, if the subjects from the analog-to-digital converter 4 are larger than the code recorded in the memory element 10, then the recording signal is stored at the recording input of the memory element 10 and the data from the analog-digital converter 4 are recorded in the memory area in which the maxima are stored.

If the data code from the analog-to-digital converter 4 is less than the code recorded in the memory element 10. then the logical 1 signal from the output is Less than the digital comparator 11 by the synchronizing signal from the third output 20 of the pulse distributor 12 switches the first D-trigger 13. Logical 0 to its inverted output, passing through the third element AND NOT 14. addresses the memory area in which the lows are stored. The comparison of the codes from the outputs of the analog-to-digital Converter 4 and the storage element 10 is repeated. If the data code from the analog-to-digital converter 4 is larger, then writing to the memory does not occur, since the D-flip-flop 13 keeps the second element And 15 closed, regardless of the output value. More than the digital comparator 11. If the data code from the analog-to-digital converter 4 less, then the signal corresponding to logical 1 from the output of Less than the digital comparator 11 passes through the OR element 16 to the D-input of the second D-flip-flop 17, which forms a synchronizing pulse from the fifth output 22 of the pulse distributor 12 at its inverse The output signal is recording.

When reading the values of the extrema from the memory element 10 to the input of the Vyb / read meter, the logical level is set to 0. prohibiting the passage of pulses from the generator 1 clock pulses 7 to the distributor 12 pulses. The control pulse at the input Reset sets the address counter 7, RS-trigger 8, the distributor of 12 pulses, the first 13 and second 17 D-flip-flops in the position corresponding to the initial recording mode. In addition, the level of logical O, established at the second output 19 of the pulse distributor 12, through the inverter 5 allows the passage of clock pulses from the first input of the TI meter through the first AND-NOT 6 element to the counting input of the address counter 7,

A zero level at the input Vyb / count prohibits the arrival of pulses from the clock 1 to the first input of the pulse distributor 12, so it does not change its state, therefore, the recording signal generated by the first and second D triggers 13 and 17 does not occur.

For each clock pulse, the state of the address counter 7 changes from the input of the TI and the data from the memory element 10 are sent to the output of the meter, the `` active pulses '' of the TI are supplied until all extrema are read, for example, to the memory of the microcomputer.

Claims (1)

Claim A voltage extreme meter containing a clock generator whose output is connected to the first input of the first AND element, the second input of which is connected to the second input of the meter, and the output is connected to the first input of the pulse distributor, the first output of which is connected to the first input of the analog-to-digital converter, outputs which are connected to the inputs of the storage element, the outputs of which are connected to the first group of inputs of the digital comparator, the second group of inputs of which are connected to the information inputs the memory element, and the second output of the digital comparator is connected to the O-input of the first D-flip-flop, the output of the storage element is connected to the output of the meter, characterized in that, in order to expand the functionality by providing sequential polling of the sources of the measured signals and at the same time determining the maximum and minimum for each measured voltage, an analog switch, a second D-flip-flop, an RS-flip-flop, the first, second and third AND-NOT elements, an inverter, a second AND element, an OR element, an address are entered into it a counter, wherein the first information outputs of the address counter are connected to the address inputs of the memory element and the analog switch, the second output of the address counter is connected to the second input of the second AND-NOT element, the first input of which is connected to the high-order input of the first information group, s-inputs of the digital comparator and with a direct output of the RS flip-flop, the R-input of which is connected to the third output of the address counter, the R-input of which is connected to the S-Vhs · ohm of the RS-flip-flop and to the third input of the meter, and the C-input of the address counter and connected to the output of the first AND-NOT element, the second input of which is connected to the first input of the meter, and the first input through the inverter is connected to the second output of the pulse distributor, the third output of which is connected to the C-input of the first D-trigger, and the D-input of the first trigger connected to the first input of the OR element and output Less digital comparator, output More than a digital comparator connected to the second input of the second element And, the first input of which is connected to the inverse output of the first D-trigger and the second input of the third element AND NOT, the first the stroke of which is connected to the output of the second INE element, and the output - with the (n + 1) -th bit of the address input of the storage element, the recording input of which is connected to the inverse output of the second D-trigger, the D-input of which is connected to the output of the OR element, the second input which is connected to the output of the second And element, the R-input of the first D-trigger is connected to the fourth output of the pulse distributor, the fifth and sixth outputs of which are connected respectively to the C- and R-bxodes of the second D-trigger, the second input of the analog-to-digital converter is connected to the output analogues of the switch, the inputs of which are the input terminals for connecting the meter measuring signal sources.