SU1425682A1 - Device for test monitoring of dicital units - Google Patents

Abstract

The invention relates to computing and is used in systems for monitoring and diagnosing digital computing devices. The purpose of the invention is to increase the productivity of the control. The device contains a control unit, a decoder, an input and output registers, two switches, a comparison unit, a mask register, an input-output mask register, a result register, a trigger trigger, an OR element. The device provides the possibility of increasing and programming the number of outputs of monitored digital nodes due to the operative reconfiguration of the structure of the device. 1 hp f-ly, 3 ill. SS

Description

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The invention relates to a decisive technique and is intended for use in systems for monitoring and diagnosing digital computing devices.

The purpose of the invention is to increase the productivity of the control.

FIG. 1 shows a block diagram of a device for test control of digital nodes; in fig. 2 - a decoder block diagram; in fig. 3 is a structural circuit of the control unit.

The device (Fig. 1) contains a decoder 1, a control unit 2, n-vhon registers 3, n registers 4 input-output masks, n registers 5 masks, n memory blocks 6, the first group of switches 7, n comparison blocks 8 , n result registers 9, second group of switches 10, monitored digital node 11, n output switches 12, n flip-flops 13, element OR 14, device reset input 15, device write input 16, device read 17, device address 18 , data bus 19, decoder 1 start-up output 20, output 21 of the initial address of the decoder 1, output 22, output 22 / Reading the state of the decoder 1, output 23 of reading the address of the decoder 1, output 24 of reading the failures of the decoder 1, a group of gate outputs 25 of the decoder 1, output 26 set to O of the input registers of the decoder 1, output 27 reset, trigger trigger the decoder 1, output 28 write masks of inputs, output 29 of the record of the string of the decoder 1, output group 30 of the result of the decoder 1, output 31 of the input-output mask of the decoder 1, input 32 of the address of the decoder 1, the first control input 33 of the decoder, the second control; iy input 34 decoder 1, groups Pu inputs 35 of the address of the decoder 1, a group of information inputs 36 of the decoder 1, a group of outputs 37 with three stable states of the decoder 1, 38 start of the control unit 2, input 39 of the address record of the control unit 2, input 40 of the state of the control unit 2, input 41 reading the address of the control unit 2, the input 42 of the reading of failures of the control unit 2, the input 43 of the reset of the control unit 2, the output 44 of the blocking of the address of the control unit 2, the output 45

Q

5 0 5 Q

five

0

allow comparison of the control unit 2, the group of outputs 46 of the address with three stable states of the control unit 2, the group of information inputs-outputs 47 of the control unit 2, the group of inputs 48 of the failure detection unit of the control unit 2.

"Decoder 1 (Fig. 2) contains a write decoder 49, a read decoder 50, a memory cell address register 51, a switch 52.

The control unit 2 (Fig. 3) contains a clock pulse generator 53, element 54, start RS-trigger 55, first switch 56, second switch 57, delay element 58, address register 59, element HE 60, address counter 61, element OR NOT 62, first element OR 63, second element OR 64, third 65 and fourth 66 switches.

The device works as follows.

Before starting, the TCA is reset. To do this, a reset signal is applied through the input 15 of the device, which is fed to the installation inputs in registers 5, -5, 4, -4, and 9, -9, and sets them. the initial state, as well as having passed through the input 43 of block 2 and the first element OR 63, sets the trigger 55 to the zero state and, after passing through the OR 14 element, sets the triggers 13 to the zero state.

The device operates in the modes of loading, testing and analyzing test results.

The organization of the load mode includes performing setup operations of the input registers to the initial state; the sub-cycle of forming the information line in the input registers 3j: 3.1 — registers 4, input-output masks; 3.2 - registers 5, masks; 3.3 - blocks 6, memory.

The input registers 3 are set to the initial state via the address inputs 35 group of the decoder 1 from the bus 18 to the control inputs of the decoder 49, which receives the address of the installation command in O of the input registers, and when a signal arrives Recording from input 33 to the gate input The decoder 49 records from the output 26. The signal is set in the O input registers.

which arrives at the installation inputs in registers 3, setting them to the zero state.

The sub-cycle of forming the information line in the input registers 3, -3 is carried out as follows.

The device data bus 19 receives a fragment of the bit information line and is set at the information inputs of registers 3. Recording occurs on the command. Selecting the input register from output 25 to that input register whose address is

addresses of the memory cell are fed through gaine 18 to decipher 49, and when a signal arrives Recording to the accelerator input of the decoder 49 from the input 16 of the device at (n + 8) the output of the decoder 49, a signal is generated to the input of the parallel register entry 51, which the address of the memory location is written to this register.

From the outputs of register 51, the address of the pth memory cell through the switch 52 is unlocked by a high level

set to the control inputs of the 5 signal from the flip-flop 55, fed through

49 ratora bus 18 when a signal arrives Recording to the gate input of the decoder 49 from the input 16 of the device. The process of loading line fragments in

a group of outputs of the address with three states of the decoder 1 per group of address inputs of blocks 6,,

The test string is written.

input registers are repeated until praz. 20 at the command Write a test line, with

the execution of which from (n + 6) -th output of the decoder 49 to the recording inputs of blocks 6 receives a recording signal, by which information is recorded in the memory cell. The specified processes of forming a line in registers 3 and rewriting it into memory blocks 6 are performed by K, and „(, times.

As a result, the generated information is set at the information inputs of registers 4 and 5, and blocks 6 (,

3.1. Overwriting information from registers 3 to registers 4 ,. In this case, the information is the control information about the masking of the input and output pins of the node 11. On the control inputs of the decoder 49

Bus 17 receives the address of the command Write I / O Mask, and when the decoder 49 arrives at the gate input from the device's device's input 16, Record at output 31 is a signal Write the input-output mask that goes to the inputs of the parallel register 4.

3.2. The rewriting of the control information line on the masking of the input pins of the node 11 of registers 3 to registers 5 is carried out similarly by the command Record input mask. With the execution of this command, the recording of information into registers 5 takes place at the entrance of output 28 from inputs 28 to the inputs of parallel recording of registers 5 of a signal. The input masks are recorded.

 3.3. In the case of rewriting information from registers 3, into blocks 6, the information is a string of test. Before writing the test string to the memory blocks using the command Writing the address of the memory cell, a record is written into the register 51 of the memory cell address. To do this, the data cell address is entered via the data bus 19 and is set at the information inputs of the register 51. Command address Write

a group of outputs of the address with three states of the decoder 1 per group of address inputs of blocks 6,,

The test string is written.

0 on command Write test string, with

five

0

five

0

five

0

five

the execution of which from (n + 6) -th output of the decoder 49 to the recording inputs of blocks 6 receives a recording signal, by which information is recorded in the memory cell. The specified processes of forming a line in registers 3 and rewriting it into memory blocks 6 are performed by K, and „(, times.

The load mode is completed by loading the test start address into the address counter 61 by the Start address command, during which the test start address from the data bus 19 is recorded through the group 47 through the counter when the recording signal from the (n + 2) -th output of the decoder 49 is received to the input counter records 61.

The test mode is set by issuing the Start command, upon receipt of which a signal is generated at the (n + 1) -th output of the decoder 49, which is fed to the S input of the start RS-trigger 55, setting it to one. The appearance of a zero potential from the inverse output of the trigger 55 through the output 44 at the control input of the switch 52 transfers its outputs to the third state, thereby blocking the receipt of the memory location address from the decoder 1.

A single potential from the direct output of the trigger 55 permits the passage of clock pulses from the output of the generator 53 through the element 54 to the input of the parallel recording of the register of the address 59. On the leading edge of the first pulse arriving at the input of the register of the address 59, the test start address is rewritten from the outputs of the address counter 61 to the register 59, from the outputs of which through the second switch 57 enters the address inputs of blocks 6. The reference value of the first line of the verification test occurs, which is from the outputs of blocks 6; enters the second group of inputs of the blocks 8, the comparison, and also, having passed through the switches 7, the formed line of test actions will go to the inputs of the monitored digital node. From the outputs of node 11 through switches 10, the reaction of node 11 goes to the first group of inputs of blocks 8,

Comparison results (О, if a failure) from the inverse outputs ix of blocks 8 (arrive at the information inputs of the flip-flops 13 ,. Record in the D-flip-flops 13 | of the comparison result and in the registers 9, the result of the node 11 reaction occurs on the leading edge of the first pulse, from the output 45 to the D-flip-flop synchronous inputs 13 and the inputs of the parallel recording of registers 9 (and the delay delayed by element 58 by the magnitude of a. The value C is defined as the sum of delays in passing information to node 11 when the latter triggers and when the node responds 11 through switches 10 (and blocks 8,. From the outputs of the flip-flops 13 (the Failure signals go through the group of the fault detection inputs 48 to the OR element 64 and the information inputs of the switch 66. Next, the device operation is determined by the values of the Failure signals

If the Failure signals are zero, then on the falling edge of the first clock pulse, coming through the NOT 60 element to the subtracting input of the address counter 61, the contents of the last one are reduced by one, and on the leading edge of the next clock pulse, is copied to the register 59 ,.c outputs the address of the next test string enters through the switch 57, the output group 46 to the address input group is blocks 6, | - 6f ,.

The testing process continues until the value of the counter 61 becomes zero or the output potential of the element OR 64 does not reach a single potential.

If the contents of counter 61 is zero, then a single signal appears at the output of the OR-NOT 62 element, which through the element OR 63 enters the

Input setting in the RS-flip-flop 55 and sets it to. zero state. The zero potential from the direct output of the trigger 5 blocks the flow of clock pulses through the element 54 and the device stops.

The test result analysis mode starts when, in the test mode, the trigger 55 is set to the zero state. For analyzing the state of the device, the device read state command is used, during which the address of this command is sent via bus 18 to the decoder 50, and when a signal appears, the read at the gate input of the decoder 50 produces a signal at its (n + 1) output coming through the output 22, to the control input of the switch 56, from the output of which through the group 47 to the bus 49 the device status code is transmitted. The status code contains two bits taken from the direct output of the 55-O trigger and the output of the OR 64-1 element. Depending on the state code (00 is the initial state of the device; 10 is the test mode; 01 is the stop on failure; 11 - no trigger trigger reset) The device user can perform the following actions. If after resetting the device the status code is / 00, then the device is defective and it needs to be repaired. If after issuing the Start command the status code is 10, then the device is in test mode and you need to take a break for the testing time, if the state code does not change after that, then the device fails. For code 00, the test is successful and you need to load the following test, while code 01 detects a mismatch with the response standard of the object being diagnosed on the input action and the following control information necessary for failure analysis can be derived: the address of the failed test line, fragments eaktsii diagnosis objects at the input action, sources of failures,

The address of the failed test line is output by the command Reading the address register, at which from the (n + 2) -th output of the decoder 50 through the output 23 of the decoder 1, the control input of the switch 65 is given a signal permitting the transfer of the address

a failed test line from register 59 through this switch to the data bus 19.

Information on the sources of all faults is displayed on the command Read faults, which are fulfilled from the (n + 3) -th output of the decoder 50 via the output 24 of the decoder 1 faults, and the control input of the switch 66 is given to allow the transmission of information from the direct outputs. D-triggers 13, -13ts through this switch to bus 19.

Claims (1)

1. A device for testing control of digital nodes, containing a control unit, a decoder, a memory unit, a comparison unit, two switches, the output group of the memory unit connected to the first input group of the comparison unit and the information input group of the first switch, the Vcode group of which is connected with the first group of outputs of the device for connection to the first group of inputs of the monitored digital node and connected to the group of information inputs of the second switch, the group of outputs of which is connected to the second group in odov comparing unit, a group of address inputs of the memory unit is connected to the group address outputs control block and a first group of decoder outputs, a first output coupled to an input start control unit, the address output lock koto rogo connected to the lock input the decoder, the second output of which is connected to the recording input of the memory unit, and the first and second synchronization inputs and device address setting group are connected to the synchronous input, the strobe input and the information encoder group of the decoder, respectively, the second group of information inputs of the decoder 1a is connected to the test inputs of the device, different that, in order to increase the control performance, n input registers (n is the number of monitored nodes), (n-1) memory blocks, n mask registers, the first group of commu units, () comparison blocks, n trigger triggers, n input-output mask registers, second group of switches, n register five 0 5 o five 0 , five 0 a result ditch, n output switches, a RSHI element, the group of outputs j-ro (j 2, n) of the memory unit is connected to the first group of inputs of the j-ro comparison unit and to the first group of information inputs of the j-ro switch of the first group, The output group of which is connected to the jth output group of the device for connecting to the jth input group of the monitored digital node and connected to the information input group of the j-ro switch of the second group, the output group of which is connected to the second input group of the j-ro comparison unit, group j-ro address block and the memory is connected to the group of outputs of the decoder, the second output of which is connected to the recording input of the j-ro memory block, the information outputs group i-ro. (i 1, p) of the input register is connected to the information inputs group of the i-ro memory block, The mask register i-ro, the I / ro register of the I / O mask, the output group of which is connected to the control inputs group of the i-ro switch of the second group, the output groups of which are connected to the information inputs group of the i-ro result register, the output groups of which are connected with a group of information inputs i- ro output switch, the output of the second and third groups of the decoder are connected respectively to the gate input input input register i and input i, input control, the output of the decoder from the third to the tenth are connected respectively to the input of the initial address, state read input , the input of the address read, the input of the failures of the control unit, the input of the setting in About the input registers, the first input of the OR element, the write input of the mask registers, the write inputs of the registers of the input-output mask, the group of controllers the i-ro switch of the first group is connected to the i-ro group of the mask register, the output is equal to the i-ro of the comparison unit connected to the i-ro input of the reset trigger, the direct output of which is connected to the iM input of the group of input inputs for the control unit failures, and the input of the zero setting of the i-ro trigger is connected to the output of the OR element, the second input of which is connected to the device reset input, the installation inputs .v About mask registers, input-output mask registers, result registers and the reset input of the control unit, the comparison resolution output of which is connected to the synchronized trigger trigger input and the input of the result registers entry, the control unit output group is connected to the input registers information input group output switches and device test inputs. 2, The device according to claim, 1, characterized in that the control unit contains a clock pulse generator element AND, element NOT, trigger, four switches, delay element, address register, address counter, element OR NOT, two elements OR, and the generator output clock pulses are connected to the first input of the element I, the direct output of the trigger trigger is connected to the first information input of the first switch, as well as to the control input of the second switch and the second input of the element AND whose output is connected to the input of the delay element and the input of pairs llelnoy register entries, addresses and not through the element from which the element through entrance vmitayuschim address counter, a group of bit outputs of the NOR is connected to a first input of the first OR gate, a second input coupled to an output of the second OR gate and a second infor the first input of the first switch, the output of the first element OR is connected to five the trigger setup zero input, the group of bit outputs of the ad- res counter is connected to the group of information inputs of the address register, the group of outputs of which is connected to the groups of information inputs of the second and third switches, the group of outputs from the first, third and fourth switches are connected to the group of information inputs an address counter and a group of outputs of a control unit; a group of outputs of a second switch is connected to a group of outputs of an address of a control unit; an input of a parallel record of an address counter is connected to the input of the address of the control unit, the installation input to the trigger trigger is connected to the trigger input of the control unit, the third input of the first element OR is connected to the reset input of the control unit, the control input of the first switch is connected to the read input of the control unit, group Fault detection inputs are connected to the inputs of the second OR element and information inputs of the fourth switch, the control input of which is connected to the fault input of the control unit, the control input of the third switch connected to the read input of the address of the control unit; the inverse output of the trigger trigger is connected to the output of the blocking address of the control unit; the output of the delay element is connected to the output of the comparison resolution of the control unit.