SU1363213A1 - Multiinput signature analyser - Google Patents

Abstract

The invention relates to computing and can be used in systems for diagnosing digital objects. The aim of the invention is to extend the functionality by interrogating a predetermined number of inputs in the period between the delivery of test actions. The analyzer contains two registers 1 and 2, the first element And 3, the counter 4, the multiplexer 5, the comparison unit 6, the signature generator 7, the trigger 8, the delay element 9, the second element 10. The signature analyzer is in operation during the period between two consecutive feeds. test effects using a multiplexer polling all the inputs of the controlled object in the range between the start and end addresses, respectively, recorded in the first and second registers. 1 il. i cl co 05 co to co

Description

The invention relates to computing and can be used in systems for diagnosing digital objects.

The aim of the invention is to extend the functionality by interrogating a predetermined number of entries in the period between the delivery of test stimuli.

The drawing shows a structural diagram of the input signature analyzer

counter 4, multiplexer 5, comparison unit 6, signature generator 7, trigger 8, delay element 9, second element 10, entries 11 and 12 of the record, respectively, of the initial and final addresses of the analyzer inputs, the second group of information inputs 13 of the analyzer clock input 14 of the analyzer , the input 15 of the initial setup of the analyzer, the input 16 of the gate of the slot, which defines the first input to be checked, switches the initial input to the information input of the signature generator 7.

The start of the test is determined by the input to the gate 16 of the recording of the test effect of a single potential signal, indicating that the test set is ready to write to the test register (not shown). In view of that.

The analyzer contains the first register 1, 10 that the second element AND 10 is located in the second register 2, the first element is AND 3, the covered state, then the recording gate passes

through the analyzer and fed to the output 20 of the synchronization of the supply of test impacts. When the recording of information into the register is completed, the signal from the input 16 of the strobe of recording the test action is removed. From the outputs of the test register, a test action is applied to the checked digital node. After completion of the transient processes associated with the switching elements of the object

test test records, the first group 20 of the control, at the inputs 17 of the analyzer, the fi-informational inputs 17 of the analyzer, the reactions of the tested node to the informational outputs 18 of the analyzer, this test action, with the output 19 of the analyzer, the output 20 of the element 9 delay arrives sigc synchronization of test stimuli. It is a switch that triggers the trigger 8 into one unit, a multi-input signature analyzer state, which results in the removal of the microprocessor-controlled output 25 of the ready signal 19, the closing controller (not shown), and the opening of the first element - which includes control of the I 3 mode element. A zero logical check, communication with external devices, a signal from the inverse output of the trigger 8 memory and the central computer, and also prohibits the parallel recording of information generating a set of test influences 4. Under the action etchik takto- Vij checked for emogo digital node. New impulses coming through the open

the first element And 3 at the counting input of the counter 4, the counter 4 successively changes its state, and on the front of each odd pulse the lower bit is set to one state, and on the front of each even pulse there is a change in the state of the bits connected to the address inputs of the multiplexer 5 and the first group of inputs of the comparison unit 6. On the front of the pulse, through the first element I 3 on the counter 4, which receives the low-order bit 4, the input of the counter 4. A single potential in the signature generator 7 occurs on the inverse output of the trigger 8, the information is shifted and compressed; The parallel loading signal by my multiplexer 5 from inputs 17 is analogous to the input of counter 4, opens the second generator to the information input form And 10 and exposes 19 a gate 7 at the output, and also a readiness signal synchronizing the recording. Information information on the information input, inputs 13, combined with the trigger data bus 8. The process described will be a microprocessor controller, the starting and ending addresses of the inputs are sequentially set, which are written to the corresponding registers 1 by the recording signals supplied to the analyzer inputs 11 and 12 and 2. Since the load signal is present at the input of the counter 4, the information from the outputs of register 1 of the starting address number is rewritten into

the counter 4, the least significant bit of which is set to 55 8 switches to the zero state, becomes the zero state. In Adney, the first element AND 3 will be closed and the national inputs of multiplexer 5 will be set; the clock pulses will be supplied. The code of the number of the initial address of the analyzer will be counted by the counter input 4. Simultaneously, the tests on the control object are synchronized by the signature analyzer.

The analyzer works as follows.

A pulse signal is supplied to the input 15 of the initial setup, which sets the driver 7 of the signatures and the trigger 8 to the zero state. The zero potential at the direct output of the trigger 8 closes the path of the passage of clock 35

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continue until the code of the current input of the analyzer, determined by the state of the bits of the counter 4 connected to the address inputs of the multiplexer 5 and the first group of inputs of the comparison unit 6, does not compare with the code of the number of the final input stored in register 2. In this case at the output of the comparison unit 6, the potential signal is zero.

the least significant bit of the counter 4, in the signature generator 7, the information is shifted and compressed by multiplexer 5 from analyzer inputs 17 to the information input of generator 7, as well as synchronization of information recording on trigger information 8. The described process will be

 8 switches to the zero state, closes the first element And 3 and closes the clock pulses to the counting input of counter 4. Simultaneously

continue until the code of the current input of the analyzer, determined by the state of the bits of the counter 4 connected to the address inputs of the multiplexer 5 and the first group of inputs of the comparison unit 6, does not compare with the code of the number of the final input stored in register 2. In this case at the output of the comparison unit 6, the potential signal is zero.

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but the second element 10 opens, at the input of counter 4, a parallel loading signal is shown, which will overwrite information from the outputs of register 1 of the number of initial inputs to counter 4, and the analyzer readiness signal will be set for further work. When the next test set is ready to write to the test register at the 16 strobe input, the test action produces a single potential signal, which will give another impact to the tested node and repeat the process described earlier.

In the event that the number of inputs scanned by the analyzer is large, by the time a single potential signal appears at input 16, analyzer readiness output 19 will have a zero signal which, when fed to the readiness input of the microprocessor controller, will put the latter into standby mode The appearance at output 19 of a single signal analyzer.

The highest efficiency of the analyzer is achieved in the case when the scanning time does not exceed the formation time of the test action, since in this case the controller does not go into the standby state.

After submitting all test actions to the checked node at the information outputs 18 of the analyzer, a signature will be formed, which, if it coincides with the reference signature, allows to conclude that the checked digital node is healthy. If the obtained and the reference signatures do not match, they proceed to localize the defective channel, which can be produced by any method.

Claims (1)

Invention Formula A multi-input signature analyzer containing a counter, a comparison unit, a multiplexer, a signature generator, a trigger, and two AND elements, the multiplexer information input group being the first group of information inputs of the analyzer, the address input group of the multi- Compiled by S. Starchikhin Tehred I. VeresKorrektor M. Maksimishinets Circulation 671 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 1 13035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 0 0 five five about 0 five The typelexer is connected to the group of bit outputs of the counter and the first group of inputs of the comparison unit, the output of the multiplexer is connected to the information input of the signature generator, the output group of which is the group of information outputs of the analyzer, characterized in that in order to extend the functionality by polling a given number of inputs in the period between the submission of test actions, the analyzer contains two registers and a delay element, with the groups of information inputs of the first and second registers of the volume The dinene and form the second group of information inputs of the analyzer, the recording inputs of the first and second registers are the recording inputs of the starting and ending addresses of the analyzer inputs, respectively, the group of the bit outputs of the first register is connected to the information input group of the parallel recording of the counter, the younger informational 1st input of the parallel the entries and the counting input of which are connected respectively to the bus of the zero potential of the analyzer and the output of the first element I, a group of bit outputs of the second register with Connected to the second group of inputs of the comparison unit, the equality output of which is connected to the information input of the trigger, the synchronization input of which is combined with the synchronization input of the signature generator and connected to the low-order bit output of the counter, the loading input of which is connected to the inverse output of the trigger, the first input of the second element I is the readiness output of the analyzer, the first and second inputs of the first element I are connected respectively to the clock input of the analyzer and the forward output of the trigger, the zero input of which is combined with the input home of the signature generator driver and connected to the input of the initial installation of the analyzer, a single trigger input is connected to the output of the delay element, whose input is connected to the output of the second element And forms the output synchronization output of the test effects of the analyzer, the second input of the second element And analyzer.