SU1223233A1 - Device for checking uniform logic units - Google Patents

Abstract

The invention relates to automation and computing and can be used in test diagnostics. The purpose of the invention is to increase the reliability of control and performance. The device contains the control unit, test generator, analysis block and detection unit. failures. When a failure is detected in one of the monitored logical nodes of the same type, this failure is detected by the failure detection unit, which identifies the number of the failed node and the type of error. In this case, a repeated monitoring cycle is performed to reveal the confirmation of the failure of the failed node. If during the next implementation of the repeated control the detected failure is confirmed, then the final address of the monitoring cycle will be the address of the test combination on which this failure occurred. With a simultaneous failure in all nodes, this failure is detected by the analysis unit, which operates on the principle of a signal analyzer. In this case, the re-control occurs again. The condition for the rejection of nodes is the presence of two failures in the organization of control cycles. 5 ILG i cl

Description

The invention relates to computing technology, in particular, to equipment for controlling logic computers, and can be used in electronics for controlling logic chips of medium and greater integration, as well as in automated systems and automated control systems for production of TECs, controllers and other logical knots.

The purpose of the invention is to increase the reliability of control and performance.

FIG. 1 shows a block diagram of the proposed device; 2 shows a control unit; in fig. 3 is a block diagram of the detection of failures; in fig. 4 is a block diagram analysis; in fig. 5 - test generator circuit.

The device contains a control block 1, a generator.2 of tests, a block 3 of analysis, a block 4 of detection of failures, monitored controlled logic nodes 5.1-5N.

The control unit (Fig. 2) contains an element W1-NOT 6, a trigger 7, a generator of 8 clock pulses, a trigger 9, an element AND 10.

The block for detecting faults (Fig. 3) contains a group of encoders 11.1 —PK encoder 12, a group of counters 13.1–13. Fault, trigger 14, element OR 15, counter 16 control cycles, fault memory block 17, indication block 18 .

The analysis unit (Fig. 4) contains a pulse distributor 19, a signature analyzer 20, a register 21, a comparison circuit 22, a reference memory block 23.

The test generator (Fig. 5) contains a parity check node 24, a buffer register 25, elements 26 and 27, a memory node 28, a register 29, a read node 30, a group of information outputs 31, a synchronization input 32, a lock input 33, an output 34 signs of control start, exit 35 signs of the control cycle, exit 36 signs of the end of the control, outputs 37 signs of the test set.

When applying the permitting level of the initial installation to a single input of the trigger 7, the latter starts. 8 clock pulse generator, which generates sync pulses, input to the input element And 10 and to the synchronization circuit of the generator 2 tests. Upon receipt from output 34 of the sign of monitoring the test of the high level generator to the single input of the trigger 9 and to the other input of the element 10, the pulse distributor 19 is reset, as well as its synchronization and synchronization of the fault memory block 17 in block 4 for detecting faults.

Trigger 7 when entering vysykikh

Levels from the output 36 of the sign of the end of control of the generator 2 tests and from the output of the sign of the failure of the memory block of failures blocks the generator of 8 clock pulses.

Upon receipt from output 36 of the sign of the end of control of the generator 2 tests of high level signals, trigger 9 blocks the operation of the distributor 19 pulses.

Upon receipt of the sync pulse at the sync pulse generator input 32, the readout node 30 generates the address of the memory node 28 and a write signal to the buffer register 25. On the output bus

memory node 28 generates a parallel code that is written to buffer register 25 by a write command. The parity control node 24 generates a resolution level when the outputs of the memory node 28 and the buffer register 25 coincide. If the outputs do not match, the parity control node 24 generates a ban level, the read node 30 is blocked at the current address and when the next clock signal arrives re-writes to the buffer register 25. By the same level, the formation of the permitting level at the output 34 of the control start feature is blocked.

The size of the binary combination used on the output bus depends on the number of inputs of controlled logical nodes of the same type 5.1-5.N.

The three star bits of the output bus of the memory node 28 perform the following functions. When reading the last test pattern, the appearance of a logical zero level in the first

the highest order corresponds to the command End of measurement at the output

36 signs end of control. The level of logical zero in the second high order of the output bus of the node 28 of the memory blocks the element And 26. This is necessary for the organization of the initial and preparatory installations for controlled logic of the same type

nodes 5.1-5.N. The output of the third most significant bit is the output 36 of the sign of the control mode of the generator 2 tests. The occurrence of the level of a logical unit in the third highest-order output bus of the node 28 of the memory indicates the beginning of the next matrix of test combinations. Each matrix of test combinations provides verification of the correctness of the execution of a certain function by controlled logical nodes of the same type 5.1-5.N. The signal from the output of the third most significant bit to register 29 records the starting address of the matrix of test patterns, which is stored there until the beginning of the next matrix. The input 33 of the generator of the generator of 2 tests provides a forced entry of the starting address of the matrix of test combinations from the register 29 to the node 30, when organizing internal control cycles. The level of the logical unit at input 33 through AND 27 permits writing to the node 30 of the reading of the starting address of the matrix of test combinations from register 29 and prohibiting the change of information

store) it in the register 29. I

Block 4 for detecting faults has K groups

inputs (where K is the number of controlled outputs of the same type of logical nodes) group cipher1) attors 11.1 - PCs that implement the expression (1), which speak about the discrepancy of information, coming to the station from the monitored nodes: (And i) - ((5.1.1 ) (5.2.1) .....

(5.N.I) V (5.1.1) (5.2.l): ....:

(5.N.1)) V VV ((5.1.i) - (5.2.1)

(5.N .i) V (5.1 .i) (5.2.i). ... (5.N. I)) V .. ...... ((5.1.K) - (5.2.K).:. (5.N.K) V (gTT7K

.2.K) .... (5.N.K)), (1)

where i, ... K; N is the number of monitored logical nodes.

At the outputs of the encoder 12, information is generated that is present at most of the outputs of the monitored nodes of the same type, according to the following expression:

JsTTTi) (3.2. I) ... (5 .N. I) V (5.1. I)

(5.2.i) ... (5.N.i) V (5.1.i) (5.2.1)

(5.N.i) V (5.1.i) (5.2.i) ... (5.N.i) (2)

When a fault is detected in one of the monitored logical nodes 5.1-5.N, Ha, the output of the corresponding encoder group 11.1-1. K appears

the level of the logical unit, which through the element OR 15 is fed to the single input of the trigger, 14. The trigger 14 is also controlled by a signal from the output of the comparison block 22 of the analysis unit. The trigger 14 generates a signal that is fed to the input of the element And 27 and to the input of the read register 29, thereby triggers

means of organizing an internal control procedure and allows the counter to operate for 16 cycles. The content of the latter is increased by one after the completion of each re-control cycle, which is set by the test generator from output 35. The counter conversion factor of 16 cycles is two.

The size of the internal control cycle is not constant and depends

on whether the detected failure of one of the controlled logical nodes 5.1-5.N is confirmed during repeated monitoring procedures. The start address of the internal control loop is always

matches the starting address of the corresponding matrix of test combinations. In the case when, during the next re-control implementation, the previously detected failure is not confirmed, the cycle ends with the last address of the matrix of test combinations. If, on the next re-control implementation, the previously detected failure also repeats, then the end address of the cycle is the address of the matrix of test combinations at which this failure occurs.

The values of the test pattern matrices themselves are not random. Each matrix contains the minimum number of test combinations, including the installation, necessary to verify the correctness of the logical operations. Upon completion. third cycle internal control

The counter 16 cycles generates a signal that sets the trigger 14 to the zero state and clears the group of counters 13.1 - 13. K failures.

Each of the counters 13.1-13.K

group faults fixes faults occurring in the corresponding controlled logical node 5.1-5.N and generates address signals for the fault memory block I7 in the presence of two

failures in one of the controlled logical nodes 5.1-r5.N. Block 17 of the memory of failures depending on the presence of signals at the outputs of the counters 13.1

13. To the group failures and at the input of the signal, to which the error signal of the comparison circuit 22 of the analysis unit 3 is received, turns on the Control lights.

Failure memory block 17 is a decoder, made in the form of a software program memory, the firmware of which corresponds to the table presented.

The zeros in the columns of the table indicate the absence of the corresponding signals and the off state of the corresponding lights of the display unit 18. The units in the columns of the table indicate the presence of the corresponding signals and the switched on state of the corresponding lights of the display unit 18.

The analysis unit 3 comprises a pulse distributor 19, a signature analyzer 20, a register 21, a comparison circuit 22, and a standard memory block 23. The initial installation is performed by the High level signal, from the output of trigger 9, arriving at the reset input of the distributor 19 pulses. From this point until the arrival of a low level at this input, when each clock pulse arrives from the AND 10 element on the pulse distributor 19, it generates pulses that control the operation of the analysis unit 3. The information inputs of the signature analyzer 20 receive information from the outputs of the encoder 12. The generated signature is supplied to the register 21 for

Toot, Marriage and generates a signal Failure at the output of the sign of failure.

The operation of the malfunction memory unit 17 is presented in the table.

storage. Signals from the outputs of the sign of the test set of generators 2 are received at the address input of memory block 23. In accordance with the address, memory block 23 generates a code arriving at the comparison circuit 22, which compares the signature stored by the paicnpe divider 19 pulse. register 21 and block 23 of memory. If the signatures do not match, a comavda is formed. The signature on the one of the address inputs of the fault memory block 17 in block 4 of the fault detection 4 is incorrect.

The device works as follows.

When applying a resolution (its Initial Setup level, the control unit 1 generates the clock pulses that go to the test generator 2x sync input, the output of which forms the required number of combinations that set up the controlled logic blocks 5.1-5.N to the initial state. Then the 2 test generator forms the resolving level. at the exit 34 of the sign of the start of control and the sync pulse of the control unit 1 is fed to the fault detection unit 4, which makes a comparison of each logical output of the same name

and generates at the outputs a parallel code corresponding to the state of the majority of inputs (majority networks). If the information on the inputs of the encoders 5 of group I1, the G2 encoder does not match, the error counters fix it, and the display unit shows the number of the logical node in which the failure occurred, and the means of organizing the internal control cycles are triggered. Internal control loops ensure the logical nodes are re-checked using the matrix of test combinations in which the fs failed. Depending on the opt-out result of the control, the device either continues the further check, or generates the signals. Scrap, Control repeat, It is also possible that all 20 monitored controlled logic, nodes 5.1-5.N failed at the same time. Such a failure will be detected only by the analysis unit 3 as a result of the discrepancy between the generated and the standard 25 signatures. In this case, the re-control procedure also occurs.

The generated signature is the result of conversion in block 3 of the analysis of the parallel code from the outputs of the encoder 12 to a sequence of combinations. It is formed after each test combination.

The condition for rejection of a controlled logical node is the presence of two failures in the organization of internal control cycles using the same matrix of dough combinations. In this case, as well as the double appearance of the wrong signature, the control automatically stops and the Marriage indication is displayed. Controlled logical nodes are recognized as valid if true:; Last signature and no indication of marriage

If the control is interrupted and there is an indication of the Control Repeat, the displayed logic block is re-monitored as part of the next monitored group.

Claims (1)

Invention Formula A device for monitoring single-type logical nodes containing a test generator, a control unit, an analysis unit and a failure detection unit. 40 45 5 y fs 20 25 zo five 0 five the control unit contains the first and second triggers, a clock pulse generator, an OR-NOT element and an AND block, the analysis block contains a signature analyzer, a pulse distributor, a register, a comparison circuit and a standard memory block, and the fault detection block contains an indication block the input of the initial installation of the device is connected to the single input of the first trigger, the output of which is connected to the start input of the clock pulse generator, the output of which is connected to the first input of the And element and the clock input of the test generator, the group of information outputs of which is connected to groups of information inputs of the same type of controlled logical nodes, the output of the element of the IPI is NOT connected to the zero input of the first trigger, the second input of the element I is connected to the output of the sign of the beginning control of the test generator and the single input of the second trigger, the zero input of which is connected to the output of the sign of the end of the test generator control and with the first input of the element OR NOT, the output of the element AND is connected to the synchronization input of the pulse distributor, the input whose reset is connected with the output of the second trigger, the first output of the pulse distributor is connected to the synchronization input of the signature analyzer, the outputs of which are connected to the information inputs of the register, the synchronization input of which is connected to the second output of the pulse distributor and the synchronization input of the comparison circuit, the first group of information inputs of which are connected to the output group the second register of the group of information inputs of the comparison circuit is connected to the group of outputs of the standard memory block, which is different in that and the reliability and performance monitoring, fault detection unit comprises a plurality of counters SRB, a storage unit failure, OR gate, the third flip-flop, a control cycle counter, encoder and a group of encoders, and the groups of outputs of controlled logical nodes are connected to the information inputs of the corresponding encoders of the group and to the groups of information inputs of the encoder, the output of which connected to the information inputs of the signature analyzer, the outputs of the group encoders are connected to the inputs of the OR element and to the counting inputs of the corresponding group failure counters, the reset inputs of which are connected to the overflow output of the control cycle counter and the zero input of the third trigger, whose single input is connected to the output of the OR element , three-trigger trigger output Connected to the resolution input of the control cycle counter and to the input, test generator resolution, the bit outputs of the group fault counters and the output of the circuit Neny connected with the address inputs of the memory unit failure, SRB output characteristic of which is connected to a second Early mouth the input of the element OR NOT, the synchronization input of the memory block of failures is connected to the output of the element AND, the group of outputs of the numbers of monitored logical nodes of the memory block of failures connected to the first group of information inputs 9 of the display unit, the second group of information inputs of which are connected to the group of outputs of signs of failures of the same type of controlled logical nodes of the memory block of failures, the output of the sign of the test set of the test generator is connected to the address input of the memory block of the standard, the output of the sign of the counter cycle the test generator is connected to the counting input of the control cycle counter. 5.1 5. g ff.H figure 1 f (j / i.H / IH-HfB fig.Z From 37 From luuippam. it . phage.5 VNIIPI Order 1715/52 Circulation 671 Random polygons pr-tie, Uzhgorod, st. Project, 4 gz H go ttrig.9 ffmyjr./ff fagL Subscription