SU1188740A2 - Device for checking logical units - Google Patents

Abstract

DEVICE FOR THE CONTROL OF LOGICAL KNOTES by author. St. No. 1024924, characterized in that, in order to increase the reliability of the control, a test signal signature analyzer and an OR element are introduced into it, the group of information outputs of the test generator is connected to the group of information inputs of the signature analyzer of test signals, the synchronization input and the zero input of which are connected respectively to the second and third outputs of the control unit, the error outputs of the signature analyzer and the test signal signature analyzer are connected respectively to the first and second inputs of the AND element LI, the output of which is connected to the third input of the control unit, the second input of the resolution of the majority block is connected to the error output of the signature analyzer of test signals.

Description

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The invention relates to computer technology, in particular, to equipment for controlling logical computers, and can be used in electronics for controlling logic chips of medium and high degree of integration, as well as in automatic complexes and automated control systems for the production of TECs, controllers and other logical blocks. .

The purpose of the invention is to increase the reliability of the control.

FIG. 1 is a diagram of the proposed device; in fig. 2 - test signal signature analyzer.

The device contains a control unit 1, a generator of 2 tests, a 3-signature analyzer, a 4-test signal signature analyzer, and a majority block 5, monitored logic nodes 6.1-6.3, and an OR 7 element.

The control block I, the generator of 2 tests and the analyzer of 3 signatures are made according to the main author. St. No. 1024924.

The test signal signature analyzer 4 has a pulse distributor 8, a signature analyzer 9, a memory register 10, a comparison circuit 11, a memory block 12, an incorrect test output 13, information inputs 14 of the test signal signature analyzers, zero input 15 and a synchronous input 16.

The majority block 5 contains an additional indication cell corresponding to the output of the incorrect analyzer test and the signatures of the test signals.

The device works with .1, in the image.

The initial installation is made by a start (high level) signal, which is fed to the input 15 of the distributor 8 pulses. From that moment until the arrival of the Stop (Low Level) command at input 15, as each sync pulse arrives at input 16, distributor 8 generates pulses that control the operation of the analyzer and test signal signatures. The same test signals from the 2 test generator as at the inputs of the controlled logical nodes 6.1-6.3 come to the information inputs of the 14 signature analyzer. The code thus generated is a signature that enters memory register 10 for storage. Comparison circuit 11 is performed at the command of the pulse distributor 8, comparing the signatures stored in memory register 10 and memory block 12. If the signatures do not match, the command "Wrong test that is output to output 13 is formed.

When the permit level is applied, the start of the control unit, the control unit 1, generates the clock pulses, which are fed to the input of the test generator 2. At the output of the test generator 2, the required number of combinations is established, which set the controlled logical nodes 6.1-6.3 to the initial state. Parallel test

The combinations are fed to the input 14 of the signature analyzer 4 test signals, where, when the generator generates 2 tests of the resolution level and the sync pulse control unit 1, they are converted into signatures and the “Wrong test when a wrong test combination appears. In this case, the monitoring procedure is interrupted and then the monitoring is repeated.

If the distortion of the test combination at the output of the generator 2 tests as a result of the influence of destabilizing factors (external interference, surges on the power supply circuits, etc.) occurs after

As the signature analyzer 4 test signals generated the correct signature, the test generator 2 generates a signal that blocks the operation of the control unit 1 until the end of the interference.

Simultaneously sync pulse unit 1

0 control 1 and start majority block 5, which compares each bit, generates a parallel code at the outputs that corresponds to majority and if the information at the inputs of the majority elements does not match, depending on the presence of sync pulses and the commands "Incorrect signature," Incorrect test displays the number of the controlled logical node "Marriage or" Control repeat. If all monitored logical nodes 6.1-63 and the generator of 2 tests are correctly functioning, there is no indication. Parallel to the code of the outputs of the majority block 5 is fed to the inputs of the analyzer 3 signatures, which converts it into a sequence of hexadecimal combinations or signature. The signature is formed after each test combination and compared with the calculated (reference) one. The control is automatically terminated when the wrong signature appears and after the last correct one.

0 Controlled logical nodes 6.1-6.3 are considered valid if the last signature is correct and there is no indication "Marriage. If the indication is "Marriage is, the displayed logical nodes are rejected. If the control is interrupted and there is an indication "Repeat control, indicated, the logical node is re-checked as part of the next control group.

Thus, a double-circuit control of test signals is organized: external and internal. The internal control loop is organized by a test signal signature analyzer. Due to this, the device has three phases of active control of test signals. The first phase takes place 5 during the formation of test signals and is carried out by the internal contour of the controller. A characteristic feature of the second phase — verification of the correctness of the tests — is carried out by the external control loop. A distinctive feature of the third phase is the blocking of controls in the presence of destabilizing factors, with the result that the control

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the incorrect test pattern is not conducted until the end of the effect of interference — the result of the interaction of the external and internal circuits.

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Claims (1)

DEVICE FOR CONTROL OF LOGICAL NODES by ed. St. No. 1024924, characterized in that, in order to increase the reliability of the control, a test signal signature analyzer and an OR element are introduced into it, and the group of information outputs of the test generator is connected to the group of information inputs of the test signal signature analyzer, the synchronization input and zeroing input of which are connected respectively to the second and third outputs of the control unit, the error outputs of the signature analyzer and the signature analyzer of the test signals are connected respectively to the first and second inputs of the OR element, you od which is connected to the third input of the control unit, the second enable input of a majority block connected to the output signal error analyzer test signatures. Fig <