SU955072A1 - Logic circuit functioning checking device - Google Patents

Description

(54) DEVICE FOR CHECKING THE FUNCTIONING OF LOGICAL SCHEMES

Claims (2)

The invention relates to computing and can be used in test diagnostics of malfunctions and control of logic circuits: typical replacement elements, digital device circuits, large integrated circuits. There are known devices for controlling circuits, which provide alternate testing of each circuit included in the control object by comparing its input signals with the output signals of the same type reference circuit, at the input of which the signals taken from the inputs of the monitored circuit of the object 1 are applied. limited functionality, since they allow the malfunction to be fixed under the condition of using the same type of reference circuit. The closest to the proposed technical entity is a device for testing the operation of logic circuits, which provides a test check of the operation of logic circuits by alternately comparing the signals of the monitored outputs of the device under test with the reference output signals in the block, comparing at the maximum operating frequency and containing the data input block , the output connected to the first input of the block of input and reference output signals, the output of which is connected through a switch to the control via the comparison unit to the display unit, the control unit connected by its outputs to the inputs of the data input unit, the input and reference output unit, the switch and the display unit, the controlled output unit whose output is connected to the second input of the comparison circuit, one input to the output of the input block, the other to the output of the control block, blocks of registers, with the input of one block of registers connected to the output of the block of input and reference output signals, and the input of another block of registers to the output of the block controlled by One of the outputs of the control register blocks are connected to the corresponding inputs of the display unit, the other outputs are connected to the inputs of the control unit, the control inputs are connected to the outputs of the control unit, and the comparison outputs are connected to the corresponding outputs of the input unit 2. A disadvantage of the known device is a large amount of time. to check that this is due to the necessity of alternately comparing the signals of the monitored outputs of the device under test with the reference output signals at each step of the device operation. In addition, the operation of the device cannot be terminated when a persistent failure is detected, such as the closure of inputs to ground, which causes a loss of time for testing a deliberately faulty circuit. The purpose of the invention is to reduce the inspection time. The goal is achieved by the fact that the device containing the display unit and the switch, the first groups of inputs and outputs of which are respectively groups of inputs and outputs of the device, and the input are connected to the output of the first memory block, the first input connected to the first output of the control unit, and the second - with the first output of the input and storage control unit, whose input is the input of the device, and a group of inputs connected to the output group of the control unit, an analysis unit and a second memory unit are entered, the first group inputs and first, second and third groups of outputs of the analysis unit are connected respectively with the second groups of outputs and inputs of the switch and the first and second groups of inputs of the display unit, the second group of inputs - with the output groups of the second memory block, and input and output - respectively the second output and the first input of the control unit, the third output of which is connected to the first input of the second memory block, and the second input to the second input of the second memory block and the output of the input and storage of control programs, the analysis block contains three groups the elements of the NOT elements, the group of elements And the group of comparison circuits, while the inputs of the elements of the first and third groups are respectively the second and first groups of inputs of the block, the outputs of the elements of the first group are connected to the second group of outputs of the block and through the elements of the second group to the first group of block outputs, the first input of each group comparison circuit is connected to the output of the corresponding element NOT the first group, the second input - with the output of the corresponding element NOT the third group and the third group of outputs of the block, and the output with the first And move respective element groups, a second input and whose output is connected respectively to the input and output unit. The control unit contains a polling pulse distributor, the first, second and third outputs of which are the first, second and third outputs of the block, the first input is connected to the first output of the clock generator, and the second input is connected to the first output of the start signal generator, the input connected to the second output of the clock pulse generator, the stop signal shaper, the first input of which is connected to the first input of the block, and the second input through the end of work signal generator with the second output of the block, V swarm output signal shaper started, the fourth output distributor interrogation pulse and the output of the stop signal are output group unit. The drawing shows the block diagram of the device. The proposed device contains a control block 1, a control program input block 2, memory blocks 3 and 4, an analysis block 5, a switch 6, an indication block 7, a test logic 8 and an input 9 of the device. The control unit I contains a polling pulse distributor 10, a generator 11 clock pulses, a start signal generator 12, a stop signal generator 13 and a job end signal generator 14. The analysis unit 5 contains the elements of HE 15 16 and 17 of the first, second and third groups, the group comparison circuits 18 and the elements of the group 19. The drawing also indicates the inputs 20 and 21 of the first and second groups of the display unit, contacts 22 and 23 of the switch 6 and the start input 24 of the start signal generator 12. The device allows to carry out a performance check of the logic circuit when checking circuit elements for switching from state “1 to state” O and vice versa. A test for a malfunction is considered, firstly, as a sequence of test service and information sets, at which the switching of signals in analysis block 5, from at least one monitored input of a healthy circuit, is different from switching signals in block 5 of a monitored circuit input with a fault, moreover, the malfunction is the closure of the monitored input of the circuit to the ground. Secondly, when the sets are fed, the signals switch at least one monitored output of a serviceable circuit, in contrast to the switching of signals in block 5 of the monitored circuit output with a fault. The control unit 1 implements a task for sampling a specific control program for the device under test from block 2 to blocks 3 and 4, generates polling pulses for blocks 3, 4 and 5, stops the test program in a clock in which the stop conditions occurred, and performed em. run test program. Unit 2 input control programs provides input and storage control programs. outputs test sequences of information input and reference output signals to block 4, and service setup signals to block 3. First memory block 3 implements installation and storage of one of the sequence of service signals and provides its parallel input to switch 6. Second memory block 4 implements em storage of one sequence of information input and sequence of reference output signals, realizes the parallel input of information input signals through block 5 through the channels of switch 6 on certain input contacts of the monitored circuit 8, provides parallel input of the reference output signals to block 5, which is designed to detect the state in which the test program is required to be stopped, and also if the monitored logic fails, it implements malfunction signals to the display block 7 and to the control unit to stop the test program control. Switch 6 provides for connection of input and output contacts of the checked logic, as well as corresponding inputs and outputs of block 5, to specific channels of the switch. Block 7 of the malfunction indication display of the device under test detects the failure with an accuracy of the contact number of the input or output checked logic. The checked logic circuit should have no more than M external logical poles (where M is the number of bits of the output registers of block 4). The device works as follows. Before the device starts operation, the test program of one of the logic circuits in binary code arrives at the input 9 of block 2. After block 2 receives a signal from block 1 allowing the reading of test sets of the control program to start, the sequence of overhead installation signals goes to memory block 3, and the sequence of information input and the sequence of reference output signals are stored in the corresponding registers of memory block 4. Then, from block 1, a polling pulse is sent to block 3, with the arrival of which parallel input sequence of service service signals into switch b occurs, and under the influence of these signals in the switch corresponding contacts switch, providing connection to the selected switch channels of the input and output contacts of the switch logic circuit 8, as well as groups of inputs and outputs of block 5. In the next time step from block 1, a polling pulse is sent to block 4, allowing parallel input of information input signals through block 5 to block 7 and through the channels of switch 6 to the input contact checked logic circuit 8. Block 5 determines the response of the monitored inputs and if at least one of the inputs of the checked logic circuit is closed to ground, it generates a signal malfunctions of this input, received in block 7 for fixing the number of the faulty input, and a signal in block 1 for stopping the test program. Simultaneously with the information signals, in block 5, other inputs are input in parallel from block 4 reference output signals that are compared with the output signals of the checked logic circuit 8. In the case of non-matching signals at least one controlled output, the non-comparison results are transmitted to block 7 to fix the number faulty output. Block I at each time step of the device operation generates a pulse of polling the results of comparing the output signals from the contacts of the circuit under test with the input reference signals of the control program, and in the case of non-comparison, block 1 receives a signal to stop the control test program. After checking the logic circuit 8 on one test, the next test is applied, and the process repeats until logic circuit 8 is checked on all tests, after which block 2 receives a stop signal at input 9. Signals acting on the outputs of block 3 the memory entered in the switch 6, switch the contacts of the switch, connect the outputs of the specified elements NOT 16 to the inputs of the logic circuit 8. The information signals coming from the memory block 4 to the element 15, change the potential level of the signals with " 1 to “Oh or noo borot The signals from the output of the element NOT 15 are fed to the input 20 of block 7 and at the same time these signals come to the first input of the comparison circuit 18 and to the input of the element NOT 16. At the output of the element NOT 16, the signals change the potential level from "O to" 1 or vice versa contact, for example, contact 22 of switch 6, is fed to the corresponding input of the checked logic circuit 8 and the input of the element 17. If the checked input of the logic circuit 8 is closed to ground, then the input potential of the element NOT 17 receives a signal potential level equal to zero, and element output NOT 17 signal coming the inlet 21 of the display unit 7. In block 7, the number of the faulty input contact will be fixed because of the incomparison between the logical values of the potentials of the signals received at inputs 21 and 20. The signals from the output of the HE element 17 also go to the second input of the comparison circuit 18, where the signals from the output of the HE element 15 and from the output of the element NOT 17 to the coincidence of the levels of potential regions “1 or“ O. The result of the comparison goes to the first input of the corresponding element I 19, to the second input of which a polling pulse is sent from the output of block I in each test cycle. If a mismatch is detected in the comparison circuit 18, the output element AND 19, the input of block 1, receives a signal to stop the test program. Thus, all inputs of logic circuit 8 are detected, closed to earth. To check the reactions of the logic circuit 8 to the reference signals, the corresponding contacts of the switch 6 open (for example, as pin 23), and the reference output signals come from the outputs of memory block 4 to the input of the HE element 15, causing the potential levels of the signals to switch from "1 to" O and vice versa at the output of the element NOT 15. Then the signals from the output of the element 15 do not enter input 20 into the display unit, where these signals are fixed. At the same time, the signals from the output of the element NOT 15 arrive at the first input of the comparison circuit 18 and the input of the element 16, the output of which is disconnected from the corresponding input of the checked logic circuit 8 by the contact 23 of the switch 6. The output signals of the logic circuit 8 arrive at the input of the element HE 17. Signals from the output of the element NOT 17 is fed through the input 21 to the display unit 7, where the comparison and fixation of the logical values of the signals arriving at the inputs 21 and 20 takes place. If the logical values of the output and reference signals are not compared, the block 7 is fixed number of the output terminal to malfunction checks emoy circuit. The signals from the output of the element NOT 17 are also fed to the second input of the comparison circuit 18, where a comparison occurs between these signals and the reference signals from the output of the element 15. When a non-comparison is detected, the signal from the output of element 4 is interrogated from the block 1 to stop test programs in the imaging unit 14. The control unit 1 operates as follows. When power is applied, the generator 11 starts up, and the first clock pulses are fed to the input of the distributor 10 and the driver 12 and start them. When a signal is applied to the input 24, the imaging unit 12 generates the sigal “Starting operation, which enters block 2, which allows reading test sets of the control program. In this case, the sequence of service setting signals goes to memory block 3, and the sequence of information input and the sequence of reference output signals are entered into the corresponding registers of memory block 4. With the arrival of the second clock pulse from the generator 11, the driver 12 removes the lock of the distributor 10 and the polling pulse enters block 3. With the arrival of this pulse, a sequence of installation service signals is parallel to the switch 6. With the arrival of the third clock pulse, another switch of the distributor is removed to the driver 12 10 and the polling pulse goes to block 4, where it permits the parallel input of information input signals to the inputs of the checked logic circuit 8, and to block 7 of the indication uu and reference output signals - in block 5. On receipt of the next clock pulse interrogation pulses to each of the subsequent time slots in the received operation unit 5 for comparing the results of the survey. In the case of non-comparison, the shaper 13 receives a signal, through which a pulse is generated for unit 2 to interrupt the test program. To continue checking the logic circuit 8, you need to re-send a signal to input 24. After checking the circuit on all tests of the control program, the end of the control program is output from block 2 to the input of block 4 to reset the memory registers of block 4 and to the input of the driver 14, which generates and generates a signal "End of work at the input of node 13. The latter produces a stop pulse of the test program and returns to its initial state the block 2. Thus, the proposed device provides a reduction in the time for checking logic circuits by stopping the test when the inputs are closed and obiaruzheii closed to the ground. In addition, the device has less equipment removal and provides control of its own units. Claim 1. A device for testing the operation of logic circuits comprising an indication unit and a switch, the first groups of inputs and outputs of which are respectively groups of inputs and outputs of the device, and the input is connected to the output of the first memory block, the control input connected to the first output of the block control and information input - with the first output of the control program input block, whose input is the input of the device, and the group of inputs is connected to the group you