SU1411693A1 - Wiring checking device - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used to automatically check the correctness of the electrical installation of electronic components. The purpose of the invention is to increase the speed and reliability of control. l This is achieved by providing a variable duration of the control cycle. The device contains address bus 1, bus 2 dgchnyh, polling register 3, task 4 register, control block 5, polling decoder 6, task decoder 7, electroplating recorder 8. Block 5 contains a register of 9 commands and states, a D-flip-flop 10, a generator of II pulses, an element 2I 12, a one-shot 13 and an element ZI-HE 14. The drawing also shows the terminals 15 of the galvanic communications recorder, the output 1.6 elements 2И 12, the output 17 of the recorder 8, the output 18 of the element ZI-NOT 14, the output 19 of the generator 11, the output 20 of the D-flip-flop 10 and the output 21 of the one-shot 13. The address and data buses can be connected to any device that can provide input of the necessary information in the control device. 5 il. ((L

Description

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I The invention relates to the field K (| entrol electrical measuring equipment- and can be used for automatic verification of the correctness of the electrical installation of electrical equipment blocks.

The purpose of the invention is to increase the speed and reliability of the control 31 by providing a variable duration of the control cycle.

Figure 1 shows the structural diagram of the device control installation; Fig. 2 is a timing diagram of the operation of the device upon detection of a spurious connection (i.e., capacitive coupling between the monitored circuits); Fig. 3 is a time chart of the operation of the device when a valid error is detected (galvanic coupling); Fig. 4 shows an embodiment of a registrar of galvanic couplings; Fig.5 diagram of the pulse generator.

The device contains the address bus 1 V: data 2, polling registers 3 and tasks: and 4, control unit 5, polling decoder f, task decoder 7, and galvanic communication recorder 8.

The polling registers 3 and tasks 4 are 1 6-bit binary-decimal counters with the possibility of pre-recording of the inssormation. In this case, the counting input and the overflow soda in register 4 of job Ye are used.

: The polling register 3 is intended to receive from the controller the number of one of the installation points selected in accordance with the programming check points of the object | control and search for a certain number of numbers when operating in the counter mode.

Register 4 of the task is intended to receive from the controller the number of another point of installation of the test object selected in accordance with the inspection program, and its storage during the monitoring cycle.

The control unit 5 is designed to ensure the functioning of the device in accordance with a predetermined algorithm and synchronize its operation with the control computer. The control unit 5 consists of a register of 9 commands and states, a D-flip-flop 10, a pulse generator 1, an element 2I 12, a single-oscillator 13 and an element ZI-IE 14.

The galvanic communications recorder 8 has terminals 15.

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The register of 9 commands and states - 4-bit, consists of four D-flip-flops. In this case, its first bit from the controller only writes, and the second to the fourth bit is only read. Register 9 is intended to transmit to the control device the installation of commands from the controller and transfer to the controller the states of the functional units of the device, reflecting the results of the monitoring process.

A single-shot 13 with a repeated triggering on the falling edge of the pulse (the pulse generated by it is negative) is intended to provide 1-1L together with a ZI-HE element 14 temporary blocking of the signal. Error arriving at the input of the fourth bit of the register 9 commands and states in the search mode zi The pulse duration of the output of the one-shot 13 (duration of the block) is determined from the condition

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where lane proi maximum possible duration of the transition process

when connected

to the control device of the mounting points of the control object, determined by the value of capacitors installed in the control object or the mounting capacitance of the circuits.

In this case, the address and 1 data buses 2 are associated with the poll register 3, the job register 4, and the register of 9 commands and states.

The output bus of the poll register 3 is connected to the inputs of the poll decoder 6, the overflow output of this register is connected to the second register input of the 9 commands and states and the R input of the D flip-flop 10, and the count input to the 16 output of element 2 and 12. Output bus Register 4 tasks connected to the inputs of the decoder 7 for

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The output of the first register bit of 9 commands and states is connected to the input of the generator 11 pulses and the S input

D-flip-flop 10, the input of this digit of this register is connected to the input of the single-oscillator 13, the output 17 of the recorder 8 galvanic couplings and the D-input of the D-flip-flop 10, and the input of the fourth bit to the output 18 of the ZI-NE element 14.

The C input of the D flip-flop 10 is connected to the output 19 of the generator 11 pulses, the first input of the ZI NE 14 and the input of the element 2I 12, the other input of which is connected to the direct output 20 of the D-flip-flop 10, the inverse output of which is connected to the second the input element. ZI-NOT 14, the third input of which is connected to the output 21 of the one-shot 13

The inputs of the electroplating recorder 8 are connected to the corresponding outputs of the poll decoder 6 and task 7.

At the same time, the address and data bus can be connected to any device that can provide input of necessary information to the control device. The most suitable for this purpose is a control computing complex (UHC), with which several control devices can operate simultaneously.

The installation control device is an integral part of the installation control system, i.e. It operates under the control of UVK and is connected with it by buses of 1 and 2 addresses and data. The program for controlling the operation of the installation control device and the program for checking the installation. The control object (verification test) is stored in the memory of the UVK and is triggered by an operator command. On the structural diagram (figure 1) UVK not shown.

The device control installation works as follows.

The verification of the installation of a control object begins with the integrity check of the circuit selected in accordance with the verification program.

In this case, using the address bus 1 and data 2, the first digit of the register 9 of commands and states enters a logical O, -blocking generator 11 of pulses (at the output 19 of which a logical O is set) and setting the S-INPUT D-flip-flop 10 to one state (logic level 1 at direct output 20). Then, using the address bus I and data 2 to poll registers 3 and task 4 in accordance with the check program

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the installation of the control object puts the numbers of points of the first circuit between which it is necessary to check for the presence of galvanic communication. Stored codes interpretation- 1,

Interrogators 6 of the survey, and Dani 7 run, are sent to the inputs of the galvanic communications recorder 8, including the corresponding switching keys. If there is a galvanic connection between the selected points at the output, the course 17 of the registrar 8 of the galvanic connection establishes a logic level O, which sets the third bit of the register of 9 commands and states to the zero state. After the status of this bit, with the help of address buses 1 and data 2, it is read and transmitted to the UVK, to the registers. polling 3 and task 4, the numbers of the next pair of points of the tested electrical circuit are entered (in accordance with the test program). If, after entering the polling registers 3 and setting 4 of the next pair of points at the output 17 of the registrar of electroplated communications, the logic level 1 is set indicates an error type of Open circuit in the installation of the tested circuit. At the same time, the input of the numbers of the remaining points of the circuit is stopped, and after you get an error fixed in the control room, the polling registers 3 and task 4 put the numbers of the next pair of points. If during the verification of the integrity of the next circuit, no open circuit is detected (i.e., the circuit being monitored is equal to), then the device proceeds to search for galvanic couplings not foreseen by the installation between the circuit under test and other circuits of the test object.

At the same time, the address number 1 and data 2 buses in the polling registers 3 and task 4 put the maximum point number of the tested circuit, and the first bit of the register of 9 commands and states is set to one. Since the blocking of the D-flip-flop 10 and the generator 11 of the pulses is removed, then after a time equal to about half the period of the pulses of the generator 11, on the code 19 of the latter a positive differential appears (from the state O to the state 1) on the single state of the D-flip-flop 10 through the element 2 and 12 is fed to the counting input of the register 3 of the survey, the contents of which increase.

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1 is per unit. At the same time, in register A the assignment remains the entered pa- ijtee number of the nth point of installation of the object 1: ontrol (the point with the maximum number for the 1TH circuit), and in register 3 of cinpoca it is the number of the point n + 1. If a negative difference (from the logical 1 state to the JtorH4ecKoro O state) is detected at the C-input of the D-trigger 10 negative differential (output state 1 to the JtorH4ecKoro O state), the logic level 1 is set to output 17, which corresponds to the absence of a galvanic the connection between the points of electrical installation of the control object with the numbers n and n + 1 and mutual capacitance to them, at which the duration of the transient process is less than the duration of the positive impulse on you-: soda 19 of the pulse generator 1, the state of the D-flip-flop 10 does not change to the exit 20 remains a logic 1). As a result, with the arrival of the next positive differential from the output

9 of the generator 11 pulses of the state) The register of the 3 polls will increase by (unit).

With a pulse frequency of: a generator 1 1 equal to 250 kHz, the value of the real capacitance between the circuits, at which the duration of the transient process is less than the duration of the positive pulse, is C 2 µF.

If, after the next increase in the obsessed register 3 polling per unit, the registrar 8 electroplating units, there was a connection between the mounting points, the numbers of which are found in the polling registers 3 and one 4, .to a negative difference that occurred at exit 17 the galvanic communications recorder 8, triggers a one-shot 13, the logic level O at output 21 of which blocks the ZI-HE element 14, preventing the signal from the Error to the fourth input of the register 9 of commands and states. At the same time, with the arrival of a negative differential on the D-flip-flop, the 10th last is set to the zero state, since by this moment there is a zero level at its C input. The inverse output of the D-flip-flop 10 with logical | 1 is present here; and element 2 and 12 is blocked, preventing the passage of successive pulses from the output 19 of the pulse generator 1I to the counting input of the poll register 3.

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If the detected presence of a connection is caused by a capacitive coupling between the mounting points (for example, there is a significant capacitor between them,

bones), then at the end of the transition

The process at the output 17 of the recorder 8 galvanic connections again sets the level of logic 1, B

As a result, with the arrival of the next negative-negative differential on the C input of the D-trigger 10, the latter is set to one, blocking the ZI-NO element 14 through the second input and removing the lock from the second input of the 2I element 12. As a result, the nearest positive differential at the output 19, the pulse generator 11 again causes the poll register 3 to increase by one. The scanning of point numbers continues until a negative pulse polling register 3 appears at the output, which sets the D trigger 10 to the zero state, blocking the count input of the poll 3 register, and also sets the second register bit of 9 commands and states to O. The zero state of the second register bit of 9 commands and

The states of the respective data bus lines 2 are transmitted to the ACU as a signal that there is no type of error communication, which leads the device to check the next circuit.

If the cause of the occurrence of the zero level at the output. 17 of the galvanic link recorder 8 is the presence of a real galvanic link between the points whose numbers are contained in the polling registers 3 and task 4, then at the end of the negative pulse at the output 21 of the one-vibrator 13 the output 17 state of the galvanic link recorder 8 does not change .

Since the blocking from the third input of the ZI-NE element 14 is cleared, the closest positive pulse of the generator of 11 pulses is the fourth bit of the register 9 of commands and states is set to O with the subsequent transfer of the state of this bit to the corresponding data lines 2 of the UHC to fix a detected communication error. (With this numbers

points between which extra communication was detected are in polling registers 3 and task 4. After that, the device is transferred to the monitoring of the integrity of the next circuit (in accordance with

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with the check program) - using the address 1 bus and data 2, the first bit of register 9 of the commands and states is set to 0, and the polling registers 3 and task 4 are assigned the numbers of the corresponding mounting points, etc. until the end of the verification program (until the end of the control test).

Claims (1)

Invention Formula A mounting control device containing address and data buses, a poll register, a task register, a galvanic communications recorder, a control unit, address and data buses are connected to the corresponding information inputs / outputs of a poll register and a register register, the first output of a galvanic register recorder Zei is connected to the first input of the control unit, the output bus of which is connected to the counting input of the polling register, the first output bus of which is connected to the second input of the control unit, the second outputs are the electroplating circuit is connected to the corresponding terminals for connecting the control object, the control unit consists of a commander and state register, a generator, a D-trigger, element 2 and one-shot, characterized in that, in order to increase the speed and reliability of the control, device 3 entered the poll decoder and the decoder is set; t, the input of the polling decoder is connected to the second output register of the poll, the output is connected to the first input of the galvanic communications recorder, the input of the task decoder is connected to the output bus of the task register, the output is connected to the second input of the galvanic communications recorder, the element is entered into the control unit ZI-NOT, the one-shot input is connected to the first input of the control unit, the first input of the register of commands and states, the D input of the D-flip-flop, the second input of the control unit is connected to the second input of the register of commands and states and the R-input of the D-flip-flop and, data inputs and outputs of the control unit are connected to the data inputs-outputs of the register of commands and conditions, the output of which is connected to the generator input and the S-input of flip-flop -B, C-input of which is connected to the first input. element 2I, the generator output and the first input of the ZI-NE element, the second input of which is connected to the inverse output of the D-flip-flop, the direct output of which is connected to the second input of the element 2I, the output of which is connected to the output of the control unit, the output of the single-vibrator is connected to the third input element ZI-NOT, the output of which is connected to m | 5th input of the register of commands and states. . v FIG. g /five f-0r EH fig 3 / 7 Rj CZho i-j -yyyy -TO s eight R EH / g FIG. five