SU1390610A1 - Device for diagnostics of data processing equipment - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in the construction of control equipment. The purpose of the invention is to increase the speed of the device. The device contains the first counter 1, fault indicator 2, sequence memory block 3

Description

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test actions, element 4, multiplexer 5, block 6 of memory of clock frequencies, block 7 of memory of admission signatures, indicator 8 fault coordinates, element OR 9, trigger 10, generator 11 clock pulses, second counter 12, shift register 13, adder 14 modulo two, divider 15, block 16 of memory of prohibited signatures, first delay element 17, indicator 18 failure, second delay element 19 Use block

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The 3,6,7,16 memory of the sequence of test actions, clock frequencies, tolerance signatures and prohibited signatures allows you to implement end-to-end continuous diagnostics of an object without stopping it for testing, ensure its operability in case of malfunctions in a controlled object, and minimize the time of diagnostics using an object's normal operating mode of about 1 slug

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The invention relates to automation and computing and can be used in the construction of control equipment.

The purpose of the invention is to increase the speed of the device,

The drawing shows a functional diagram of a device for diagnosing data processing equipment,

The device contains the first counter 1, fault indicator 2, memory test sequence block 3, AND 4, multiplexer 5, clock memory 6, block 7 of the tolerance signatures, indicator 8 fault coordinates, OR element 9, trigger 10, a clock generator 11, a second counter 12, a shift register 13, an adder 14 modulo divider 15, a block of 16 memory of prohibited signatures, a first delay element 17, a fault indicator 18, a second delay element 19.

The control object 20, not the entrance to the device, contains multiplexers 21-25 and data processing nodes 26-30.

The device is configured for each control object

When a control object is changed, the old ones are extracted from the sockets and the new m1-Circhem of memory blocks are installed, in which the following information is programmed into the memory block 3 of the sequence of test actions, the search algorithm is entered

malfunctions, according to which the control points are viewed in the sequence of passing information through the circuits from the object's input: 20 control per output and each circuit separately, regardless of their design placement on the processing nodes; In block 7 of the memory of the per-signature signatures, at each address corresponding to the coordinates of the control point, the codes of the per-signature signatures are entered

Block 16 of the memory of forbidden signatures may not be replaced when changing the diagnostic object, since it contains permanent signatures, the presence of which excludes the passage of data through the diagnostic object (this is the signature parameter of the logical zero and one). The same signatures can be entered at the addresses of some checkpoints of the memory block of admission signatures where it is impossible to obtain stable signatures due to a random law of data change or, on the contrary, it is necessary to register a stable logical O or G c

The program Ipov of the memory block 7 of tolerance signatures is performed as follows: at the address consisting of two parts of the signature code and the checkpoint coordinate code, zero is written, and so on for all of the following signatures without changing the checkpoint address, then the checkpoint address is incremented per unit and record the following tolerance signatures. A block of 16 LAMs of forbidden signatures is programmed in the opposite way: units are written to addresses corresponding to the codes of prohibited signatures, and to the rest, to zero. Such a memory organization allows one to disconnect from the use of comparison schemes when analyzing the original signature from the reference one and to increase the efficiency of the use of the ROM.

The device works as follows.

In the initial state, the first counter 1 is reset to zero, at its outputs there are logical zeros that are fed to the address input of the memory block 3 of the sequence of test actions. At the output of block 3, a code written at the zero address appears, defining the coordinates of the initial control point. This code goes in parallel to the address inputs of the following blocks: multiplexers 21-25 control points of the control object, where the code determines the code of the control point, multiplexer, 5, where the code determines the cell number, block 6 of the memory of clock frequencies of control points, the code from the code which determines the clock frequency of the checkpoint, the memory block 7 of the admission signatures, where the incoming code selects the allowed tolerance signatures for each checkpoint and on the address inputs of the indicator 8 fault coordinates, which are raets when the signal output from the OR gate 9 in the event of a malfunction.

The device is in this state before the Start trigger signal arrives, which makes the initial synchronization of the control object with the device (this signal, for example, can be a cyclically emitted signal. Beginning of an information data frame). which is performed by a Stop or Reset signal, the signal from the output of trigger 10 triggers a generator 11, which provides a reference frequency to the input of the second counter 12 with a variable division factor. The division factor, and hence the frequency from the output of the counter 12

are determined by the code arriving at its inputs of setting the conversion factor from the output of block 6 of the clock frequency memory of control points,

From the output of the counter 12, the clock pulses arrive at the clock input of the shift register 13, which circulates the diagnostic

information received from the control point through multiplexer 5 to the input of the adder 14 modulo two, which forms a backward non-linear connection, through the fact that the inputs

adder 14 modulo two are connected (for example, with 16, 12, 9 and 7) outputs of the shift register 13, the signature register. Clock pulses from the output of the counter} -2 are also fed to the input of a divider 15 having a constant division factor (for example, equal to 65535 to perform a complete enumeration of logical states for a 16-bit shift register), since the division factor of divider 15 is constant, then the increase or decrease in the time for obtaining the convolution: the diagnostic information is determined by the frequency from the output of the counter 12.

At the moment of termination of the convolution from the overflow output of the divider 15, a Strobe signal appears, allowing reading of information from the outputs of the memory blocks of the tolerant 7 and prohibited

16 alarms If at the address consisting of two parts (signature code p of the checkpoint coordinate code) logical 0 is recorded in tolerance signature block 7, the signature has entered the tolerance zone, then after a time equal to the activation time of the tolerance signature memory and the element OR 9 (approximately

40 not), at the output of the first element

A 17-delay signal appears at its input from the overflow output of divider 15. This signal zeroes the shift register 13 and enters the input of the first counter 1, the contents of which are incremented by one. Thereafter, the collection of diagnostic information starts from the next checkpoint. The polling of all control points is repeated cyclically until a fault occurs. In this case, the Stop signal arriving at the control input of the first element

17 delays, sanpeaiaeT issue a signal to switch the first counter 1 o

If the signature of any control point is not included in the tolerance zone, then the output of the memory block of the pre-launch signatures appears logical 1 (Stop signal), which turns on the indicator 18 and after passing OR 9, enters the sync input of the indicator The 8 coordinates of the malfunction, as a result, the cell number and the reference point number are displayed on it. In parallel, the Stop signal is fed to the input of the trigger 10 and switches it to the zero state, as a result, the signal at its output disappears, which stops the generation of pulses from the generator 11. The signal from the output of the OR element 9 also enters the input of the second delay element 19, the delay time of which is determined There is no time to display the coordinates of the fault. A reset signal appears through the delay time at the output of the second delay element 19, which zeroed counter 1, divider 15, and through it the shift register 13, counter 12, and trigger 10. The device goes into the Start signal waiting mode from control object 20 upon its arrival, it turns on the generator 11, having performed the initial synchronization of the device with the control object. On the Reset signal, the output of the element OR 9 again appears logical O, the indicators 18 and 8 go out.

If the repeated polling of control points fails to rectify itself and requires operator intervention, the digits indicating the location of the fault light up and go out, their burning time is determined by the delay time for which the second delay element 19 is set (for example, 5s), and to which they go out, is determined by the removal of the faulty reference point from the input (for example, 0-3 s). There may be cases of using prohibited signatures as admissions (for example, the signal at some test point should be only logical 1 and no other, or vice versa). In this case, a logical O from the output of the memory block 7 of the admitted signatures corresponding to the tolerant signature is input to the selection of the memory block 16 of prohibited signatures and eliminates the appearance of information at its output, preventing the failure indicator 2 from lighting up. If the signature of the control point is prohibited and does not enter the allowable zone, the output of block 16

The Q memory of prohibited signatures appears logical 1, which includes fault indicators 2 and fault coordinates 8, which begin to flicker, as in the considered case with a signature not included in the tolerance zone.

Claims (1)

Invention Formula 0 A device for diagnosing data processing equipment, containing a shift register, divider, clock generator, modulo two adder, an NL element, trigger 5 and the error indicator, with a single trigger output connected to the trigger input of the clock, the group of inputs of the modulo two adder is connected to the group of bits , the outputs of the shift register, the output of the modulo two adder is connected to the information input of the shift register, the single trigger input is the start input of the device, characterized in that 5 | increase the speed of the device, two counters, memory blocks of a sequence of test actions, clock frequencies, tolerance signatures and forbidden signatures, two delay elements, an AND element, a fault indicator and a fault coordinate indicator, and the information output of the first counter are connected to the address the input of the memory block of the sequence of test actions, the information output of which is connected to the information input of the indicator of the fault coordinate, the address input of the memory block 0 clock frequencies and the higher bits of the address input of the memory block of tolerant signatures, the multiplexer output is connected to the input of an adder modulo two, the information output of the shift hinge register is connected to the address input of the memory of forbidden signatures and the younger bits of the address input of the memory block of the tolerant 0 signatures, the information output of which is connected to the input of the fault indicator, the first input of the OR element and the input of the block of memory of prohibited signatures, the information output of which is connected to the information input of the failure indicator and the second input of the OR element, the output of which is first the zero input of the trigger and the inverted input of the element I, the output of which is connected to the installation input of the shift register and the counting input of the first counter, the generator output clock pulses coupled to the counting input of the second counter, the output the first delay element, the output of which is connected to the direct input of the AND element, the output of the OR element through the second delay element is connected to the installation inputs of the divider of the first and second counters and the second zero trigger input, the lower bits of the information output of the memory block of the sequence of test actions form the information output devices for connecting to the input a task number of control points of the control object, the higher bits of the information output of the memory block of the sequence of test actions connected to the control input of the multiplexer, the group of information inputs of which forms the overflow of which is connected to the clock input of the shift register and the 20 r Pyf ny information inputs by the device input of the divider; the output of the overflow for connection to the outputs of the object is connected to the sample input of the memory of the permissible signatures, the clock input of the block of m forbidden signatures and input 25 This control, the information block of the clock memory is connected to the input of the task of the conversion factor of the second counter. the first delay element, the output of which is connected to the direct input of the AND element, the output of the OR element through the second delay element is connected to the installation inputs of the divider of the first and second counters and the second zero trigger input, the lower bits of the information output of the memory block of the sequence of test actions form the information output devices for connecting to the input a task number of control points of the control object, the higher bits of the information output of the memory block of the sequence of test actions connected to the control input of the multiplexer, the group of information inputs of which forms r Pyf ny information inputs of the device for connection to the outputs of the object r Pyf ny information inputs of the device for connection to the outputs of the object This control, the information block of the clock memory is connected to the input of the task of the conversion factor of the second counter.