SU1070562A1 - Device for checking logic units - Google Patents

Description

2. The device according to claim 1, from which the control unit contains the first switch connected to the first output of the common bus device, the second and third pins to the corresponding first and second inputs of the first trigger connected to the output of the first input of the element OR connected by a second input to the input of the unit, output to the third output of the unit and

with the input of the first delay element connected by the output directly to the second output of 1 block, and through the second delay element to the fourth output of the block, the first output of which is connected to the output of the second trigger connected to the first and second inputs, respectively, to the first and second outputs of the second switch connected to the third output of the common bus device.

Ieobretene relates to computing and can be used dL control units of logical means of computer technology. A device for monitoring and diagnostics of logic blocks, containing a test master, is connected by outputs to the inputs of a controlled logic block, the outputs of which are connected to the inputs of the signature analyzer IIj. The disadvantage of this device is the low speed due to the need for a sequential polling of the logic of all the outputs of the monitored block to obtain signatures for each of them and the manual process of comparing a large number of signatures with those specified in the technical documentation of the controlled logic block. Closest to the present invention is a device for control logic blocks, comprising a signature analyzer connected by outputs to the inputs of the first indication unit, first input — to the first output of the control unit, a pulse generator, the input of which is connected to the second output of the control unit, test setter, connected to the input the third output of the control unit, and the first outputs - with corresponding terminals for connecting the inputs of the controlled logic unit 2. A disadvantage of the known device is limited functional capabilities, due to the monitoring of the result of passing the entire set of tests, and not by individual tests, as well as the lack of information about the state of the inputs and outputs of the controlled logic block for each of the tests, which does not allow troubleshoot (diagnostic unit). The purpose of the invention is to expand the functionality of the device., The goal is to identify the device logical blocks containing a signature analyzer connected by outputs to the inputs of the first display unit, first input to the first output of the control unit, a pulse generator, whose input is connected to the second output of the control unit, test setter connected to the third output of the control unit, first outputs - with the corresponding terminals for connecting the inputs of the controlled logic unit; a second display unit, a comparison unit and a shift register connected by the output to the second input / signal are entered about the analyzer, the first input and - with the first 14 output of the control unit, the second input - with the output of the pulse generator and the third input of the signature analyzer, the third input - with the fourth output of the control unit, the fourth inputs with the appropriate terminals for connecting the outputs of the monitored logic unit and with the first inputs of the second display unit, the fifth inputs with the corresponding terminals for connecting the inputs of the controlled logic unit and the second inputs of the second display unit; the first inputs of the unit are compared are connected to corresponding second setpoint vyhs s test, the second input - to the respective outputs of the signature analyzer and the output to the input of the control unit. The control unit contains the first switch connected to the first output with the common bus of the device, the second and third outputs to the corresponding first and second inputs of the first trigger connected to the first input of the OR element connected to the input and the block by the second input, to the third output. block and with the input of the first delay element connected by the output directly to the second output of the block, and through the second delay element to the fourth output of the block, the first output of which is connected to the output of the second trigger connected by the first and second inputs respectively to the first and second pins of the second switch, connected to the third output of the common bus device. FIG. 1 shows a block-cxet-ia device; in fig. 2 - functional on the scheme of the control unit. The device for monitoring the logic blocks 1 comprises a control block 2, a signature analyzer 3, a first indication block 4, a test setting unit 5, a pulse generator 6, a shift register 7, a comparison unit 8, a second display unit 9. The control unit 2 contains the first 10 and second 11 switches, the first 12 and second 13 triggers, the elements OR 14, the first Is and the second 16 delay elements. The outputs of the signature analyzer 3 are connected to the inputs of the first 4-indication unit, and the first input is connected to the first output of the control unit 2. The input of the generator 6 pulses is connected to the second outputs of control unit 2. The input of the setter of 5 tests is connected to the third output, control unit 2, and its first outputs are connected to the corresponding terminals for connecting the inputs of control unit logical unit 1. Output of the shift register 7 dinene with the second input of the signature analyzer 3, the first input — with the first output of the control unit 2, the second input — with a generator of 6 pulses and the third input of the signature analyzer, the third input, with the fourth output of the control unit 2, the fourth inputs — with otvetstvugadimi terminals for connecting the outputs of logical one controllable unit 1, n Tide inputs - with corresponding klem1 s for connecting inputs controlled logic unit 1 and the second inputs of the second display unit 9. The first inputs of the comparison unit 8 are connected to the corresponding second outputs of the test setter 5, the second inputs to the corresponding outputs of the signature analyzer 3, and the output to the input of the control unit 2. The device works as follows. The control unit 2 generates an initial installation signal; which sets the shift register 7 and the signature analyzer 3 to the initial states. The test setter 5 sets the first test information to the monitored unit 1. From the outlets of the monitored block 1, the information is fed to the inputs of the shift register 7 and is inputted from the control unit 2 by the Input signal. Block 9 displays information on the findings of the product. On a signal Output from control unit 2, generator 6 outputs a burst of pulses, the number of which is equal to the number of outputs of the monitored product, to inputs of blocks 3 and 7. From the output of the shift register, the outputs of block 1 are written sequentially in time to the signature analyzer 3. 3, the information in the compressed cm form goes to the first inputs of the comparison unit 8, at the other inputs of which at this time the reference signal of the first test is present. In the case of a comparison, unit 8 issues a signal to control unit 2 for issuing a second test from test setter 5, which then issues a second test. The information of the second test is rewritten to register 7, shifted to signature analyzer 3, compared with the reference signature in block 8, and the result of the signature is displayed in block 4, etc. As a result of the implementation of the entire control program on the signature analyzer 3, the resulting signature is fixed, the value of which is compared with the reference value given in the specifications for the monitored unit, and a conclusion is made about its operability. In the event of a malfunction in the controlled product, the comparison unit 8 does not issue a signaling signal for the task of the next test. According to the information on the first 4 and second 9 display units, the test is determined, on which the fault is fixed, and the logic signals at the inputs of the monitored logic unit 1 in this test. The information obtained is the initial one, according to the fault. The control unit 2 operates in a slightly jgyjcmriM manner. Pressing the switch 11 from the output of the flip-flop 13 generates a pulse. The initial setting, which, entering blocks 7 and 3, sets them to the initial state. By pressing the switch 10 trigger 12 generates a pulse that passes through the element OR 14 and enters the unit 5 to the test output. After a delay on element 15, this pulse is fed to register 7 as an input signal. After the next delays on the element 16, the signal enters the block to start the generator of 6 pulses.

Signature analyzer 3 is a modulo-two serially connected modulator and a shift register, with a controlled sequence being fed to the first input and information from the outputs of the last and intermediate bit to the register to the other two.

From 9

Thus, the introduction of the shift register 7 and blocks 8 and 9 makes it possible to troubleshoot the monitored block 1, as it provides information on the test, which is detected malfunction, and logical states of the controlled block 1 on this test, which expands em device functionality.

On 5

At 7.3

Claims (2)

1. DEVICE FOR CONTROL OF LOGIC BLOCKS, comprising a signature analyzer connected by outputs to the inputs of the first display unit, the first input to the first output of the control unit, a pulse generator whose input is connected to the second output of the control unit, a test drive connected to the input with the third output of the control unit, the first outputs of the terminals for the inputs of the monitored unit are distinguished by the corresponding connection of the logical unit in that, in order to expand the functionality of the device, it is introduced The second display unit, the comparison unit and the shift register are connected by the output to the second signature analyzer, the input is the first control output, the second input is the input of the first unit - with the output of the pulse generator and with the third input cm of the signature analyzer, the third input - with the fourth output of the control unit, fourth inputs - with the corresponding terminals for connecting the outputs of the controlled logic unit and the first inputs of the second display unit, fifth inputs - with the corresponding terminals for connecting inputs controlled logical. unit and with the second inputs of the second display unit, the first inputs of the comparison unit are connected to the corresponding second outputs of the test setter, the second inputs to the corresponding outputs of the signature analyzer, and the output to the input of the control unit. tPut! 2. The device according to claim 1, characterized in that the control unit comprises a first switch connected by a first blanket to a common bus of the device, second and third terminals with corresponding first and second inputs of a first trigger connected by an output to the first input of the element OR, connected by the second input to the input of the block, the output - with the third output of the block and the input of the first delay element connected by the output directly to the second output of the block, and through the second delay element - with the fourth output of the block, the first output of which connected to the output of the second trigger connected by the first and second inputs, respectively, with the first and second terminals of the second switch connected by the third terminal to the device common bus.