SU1183972A1 - Device for simulating failures of digital equipment - Google Patents

Abstract

A DEVICE FOR SIMULATION OF DISCRETE EQUIPMENT FAILURES, containing a memory block, a register, a defect decoder, a defect driver and a switch, the switch outputs form a group of information outputs of the device, the group of information inputs of the device are connected to the first one, the group of information inputs of the switch, the group of outputs of the defect generator are connected to the second group of information inputs of the switch, the information outputs of the memory block are connected to the information inputs of the register, the outputs of which are connected Enen with the inputs of the defect decoder, the outputs of which are connected to the inputs of the defect builder, characterized in that, in order to expand its functionality by providing a simulated failure mode, the simulation task setting block, the comparison circuit, the element NOT, the element OR, the element are entered into it. And, a delay element, a cycle counter and a channel number decoder, the group of outputs for specifying the channel number of the block specifying the simulation mode is connected to the inputs of the decoder for the channel number, the outputs of which are connected to the control and the switch inputs, the output group of the cycle number of the simulation mode setting unit is connected to the first group of information inputs of the comparison circuit, the output of which is connected to the first input of the I element, the clock input of the device is connected to the counting input of the cycle counter and through the HE element to the clock w input of the comparison circuit , the group of information outputs of the cycle counter is connected to the second group of information inputs of the comparison circuit, the output of the block of the task of the simulation mode is connected to the second input of the element I, the output of which is cx Connected with the first input of the OR element and through the delay element of the OO with the zero inputs of the cycSR counter and register, the output of the block of the imitation mode setting block N1 is connected to the second input of the OR element, the output of which is connected to the block access input and the neutral input of the channel number decoder, group The address outputs of the imitation mode setting unit are connected to the group of address inputs of the memory block.

Description

one

The invention relates to computing, in particular, to devices that simulate failures and failures of hardware of computing systems, and can be used to debug and monitor hardware and software tools of a computing system designed to protect the system from failures, failures and failures.

The purpose of the invention is to expand the functionality of the device by providing a simulated failure mode.

The drawing shows a block diagram of the proposed device.

The device consists of a switch 1, a decoder 2 channel numbers, a driver 3 defects, a counter of 4 cycles, a NOT 5 element, a comparison circuit 6, an AND 7 element, an OR 8 element, a delay element 9, a simulation mode setting unit 10, a memory unit 11 , register 12, decoder 13 defect.

The device works as follows.

The user connects the information inputs and outputs of the device to the corresponding outputs and inputs of discrete hardware, to which a defect must be inserted, and the clock input of the device connects to the synchronization output of the specified discrete hardware.

Before launching the monitored equipment, the channel number is ordered from block 10 of the imitation mode setting, in which the defect must be imitated, the imitation mode (failure or failure), the cell address of the memory block 11, in which the test action is stored at the appropriate scale and, imit The cycle number of the equipment operation, during which it is required to simulate a defect. The listed symptoms are stored in block 10 of the imitation mode setting during the entire switch on of the monitored equipment.

The information containing the number of the switched channel from the group of outputs for specifying the channel number of the block 10 specifying the simulation mode is fed to the inputs of the decoder 2 of the channel number. The number of the work cycle during which you want to simulate a failure is given from the output group

839722

the cycle numbers from block 10 of the simulation mode and enters the first information inputs of the comparison circuit 6, the second information inputs

5 of which are connected with the information outputs of the counter of 4 cycles, the operation of which occurs upon receipt of impulses to the counting input of the counter 4 from the clock

About the input of the device connected to the corresponding output of the controlled discrete equipment. The same pulses coming through the element NOT 5 to the clock input

15 of the comparison circuit 6, a comparison of the comparison circuit 6 is performed. With the equivalence of information received at the first and second information inputs of the comparison circuit 6,

20, the output of the latter is formed by a signal arriving at the first input of the element AND 7, the second input of which is the output of the block 10 of the job of the simulation mode. Signal,

25 formed at the output of the element 7, goes to the first input of the element OR 8 and through the delay element 9 to the inputs of zeroing the counter of 4 cycles and the register 12. To the second input

The 30th element of OR 8 receives a signal about the presence of a failure simulation mode from the output of block 10, from whose address outputs information is sent to the address inputs of memory block 11, to the access input of which a signal is generated, which is output by the element OR 8 and serves for gating as a block 11 memories and a decoder 2 numbers

40 channels, the outputs of which are connected to the control inputs of switch 1. Reformation from the outputs of memory block 11 through register 12 is fed to the inputs of the decoder 13

45 defect, as a result of which one of the outputs of the decoder 1 3 is excited. Through the signal appearing on one of the outputs of the decoder 13 defects, which are

The 50 inputs of the imaging unit 3 defects, the output of the imaging unit generates a defect of the type ordered by the user, such as open, short circuit, clock frequency, single 55 pulse, etc. The generated defect goes to the second group of information inputs of the switch 1 and then to the ordered output of the device.

Claims (1)

A device for simulating failures of a discrete device, comprising a memory unit, a register, a defect decoder, a defect driver and a switch, the switch outputs forming a group of information outputs of the device, a group of information inputs of the device connected to the first, a group of information inputs of the switch, a group of outputs of the defect generator connected to the second a group of information inputs of the switch, the information outputs of the memory block are connected to the information inputs of the register, the outputs of which are connected to defect rows decoder, which outputs are connected to inputs shaper defect, characterized in that, in order to expand its capabilities by providing the failure mode simulation, it entered simulation mode setting unit, the comparison circuit, NOT element, element OR, AND element, delay element, cycle counter, and channel number decoder, the group of outputs of setting the channel number of the simulation mode setting unit block connected to the group of inputs of the channel number decoder whose outputs are connected to the control inputs of the switch, the group of outputs of the cycle number of the simulation mode setting unit is connected with the first group of information inputs of the comparison circuit, the output of which is connected to the first input of the AND element, the clock input of the device is connected to the counting input of the loop counter and through the element NOT to the clock the input of the comparison circuit, the group of information outputs of the cycle counter is connected to the second group of information inputs of the comparison circuit, the failure output of the simulation mode setting unit is connected to the second input of the AND element, the output of which is connected to the first input of the OR element and through the delay element with the inputs of zeroing the cycle counter and register , the failure output of the simulation mode setting unit is connected to the second input of the OR element, the output of which is connected to the access input of the memory unit and the gating input of the channel number decoder, address group the output of the unit for setting the simulation mode is connected to the group of address inputs of the memory unit.