SU1451702A1 - Device for simulating failures of discrete apparatus - Google Patents

Abstract

The invention relates to computing, namely, devices that simulate failures and failures of hardware of the computing system. The aim of the invention is to expand the functionality of the device by allowing the variation of the duration of the fault and the synchronization of the generation of the fault with external signals from the elements of the monitored equipment. The device contains an IPI-NOT 1 element, a channel number decoder 2, a defect former 3, a counter 4, a comparison block 5, a delay element 6, an AND 7 element, three elements OR 8-10, a memory block 11, a register 12, de-i encoder 13 defects, two switches 14, 15, two elements NOT 16, 17, two triggers 18, 19, block 20 of setting the simulation mode. The device can operate in three modes of 1 sbetition: in the mode of imitation of a single sbt of a given duration, starting with the cycle, the number of which is specified in block 20 of the task of the imitation mode; in the mode of simulating a single failure of a given duration when an external signal is received; in the mode of periodic simulation of the failure of a given duration, and the time interval between failures is specified by the code of the cycle number from the block 20 of the task of the simulation mode. 1 il. P I SL 4 SP | about tc

Description

This invention relates to computing technology, and to devices that mimic the failures and failures of hardware computational tools; system.

The aim of the invention is to expand the functionality of the device by providing the possibility of changing the duration of the fault and synchronizing the generation of the fault with external signals from the elements of the monitored equipment.

Diagram of the device shown in the drawing.

The device contains an element OR - NOT 1, a decoder 2 of the channel number, a former of defect 3, a counter A, a comparison block 5, a delay element 6, an AND 7 element, three elements OR 8-10, a memory block 11, a register 12, a decoder 13 of a defect , two switches 14 and 15., two elements NOT 16, 17 two triggers 18 and 19, a block-20 setting of the simulation mode, a group of 21 informational outputs of the device, a group of 22 informational inputs of the device, two inputs 23 and 24 of starting the device.

The device works as follows.

The consumer connects the information inputs and outputs of the device to the corresponding outputs and inputs of discrete equipment, to which a defect must be inserted, and the clock input of the device connects to the synchronizing output of the indicated discrete equipment.

Before starting the monitored device, the channel number is set from the simulation mode setting unit 20, the TqpoM needs to simulate a defect, the simulation mode (failure or failure), the address of the memory unit 11 in which the test action is stored, the number the cycle of the equipment, starting with which it is necessary to simulate the defect, and the code of the duration of the failure. The listed gfiznaki are stored in the block 20 setting imitation modes during the entire switching on of the monitored equipment.

The device can operate in three modes of simulated failure: a mode of simulating a single failure of a given duration, starting with the clock number that is specified in block 20 of the task

imitation mode; simulate a single failure of a given duration when an external signal is received; a periodic simulation mode of a predetermined duration, and the time interval between failures is specified by the tact number code from the simulation task setting unit 20.

In each mode, the initial setup of the device is performed using the initial setup signal coming from block 20, the counter trigger 19 is set to the zero state, and the trigger 18 is set to the single state. In this case, from the direct output of the trigger 18 to the first input of the element OR 10, a single level arrives, to the second input - a signal of the zero level from the output of the comparison unit 5. From the output of the element OR 10, the signal through the delay line sets the counter 4 to the zero state, prohibiting the counting of cycles. The no-fault signal from the output of the trigger 19 is fed to the control input of the switch 14, and through the switch 14 to the second group of inputs of block 5 comparison the code of the number of the clock from the outputs of block 20 is received. Dani imitation mode.

To set the first mode, it is necessary from block 20 to set the value of the single-time mode signal, equal to 0 s. The device start input 23 is connected to the output of the element of the controlled equipment, the signal from which starts the counting of clock cycles before the start of the simulated failure. Input 24 is not used (signal 24 is zero),

The start signal can be issued manually before the start of the monitored equipment from block 20. (signal of a single failure mode), while the device input 23 is not used.

. The signal arriving at the device input 23 passes to the input of the element OR 9. The signal generated at the output of the element OR 9 enters the input of the zero-setting of the counting trigger 18, with the result that the zero-level signal is fed to the first input of the element: nta OR 10, the second input of which receives a signal from the output of unit 5 of the comparison. From the output of the SHSh 10 element, the signal is fed to the input of zeroing the counter 4 and allows

countdown cycles. Since the clock pulses arrive at the counting input of the counter 4, as it arrives, its contents increase by one. Through the NOT element 16, the same pulses interrogate the comparison unit 5. When the information that comes to the first and second groups of information inputs of comparison unit 5 is equivalent, the latter generates a signal that arrives at the input of the OR-NOT element, on which code the signal is generated, sets the counting trigger 19 to the state 1 ( 18 and 19 are taken with inverse dynamic inputs).

From the output of the trigger 19, the presence signal is fed to the control input of the switch 14, which results in the second group of inputs of the comparison circuit receiving the code for the duration of the failure from the output group of the block 20. The output signal from the trigger 19 also goes to the first input of the And 7 element , the second input of which is connected to the output of the mode of the block of the task 20 of the simulation mode. The signal generated at the output of the element And 7, is fed to the first input of the element OR 8, at which input the signal about the presence of the failure simulation mode from the block 20 of the simulation mode is received. The signal generated at the output of the element OR 8 is fed to the input of the gating of the memory block 11 and to the input of the gating of the channel number decoder and through the element NOT 17 to the input of the nulling, register 12, allowing writing to it. The decoder of the channel number in accordance with the code arriving at its inputs from the output group of the scr.) On the channel of the simulation mode setting unit 20 selects the channel of the switch 15 to which the fault should be inserted. The test action read from the memory block 11 through the register 12 is applied to the decoder 13 defects.

By means of a signal excited at one of the outputs of the decoder .13 defects, which are the inputs of the imaging unit 3, an ordered defect is generated at the output of the imaging unit 3, which is fed to the group of information inputs of the switch 15 and further to the ordered output of the device.

A signal from the output of the comparison unit 5 also enters the first input of the element OR 10. The pulse generated by g at the output of the element OR 10 is fed to the input of the installation of the counter 4, as a result of which the counter is zeroed. When the next clock pulse arrives, the counter starts counting the duration of the fault from 10 times. When the information arriving at the first and second inputs of the comparison unit is equivalent, the last one generates a signal that switches the counting 15 flip-flop 19 to the state O. The receipt of a fault on the ordered channel is stopped.

At the moment when the trigger 19 is switched, the signal coming from the direct 20 output of the trigger 19 to the counting input of the trigger 18 switches the trigger 18. The signal from the direct output of the trigger 18 through the OR 10 element comes as a zero signal 25 of the counter, blocking its operation. The circuit is reset. When the next signal arrives at the input 23, the operation cycle of the device is repeated.

30 In order to work in the second mode 2, it is necessary to set from block 20 the value of the signal of the single failure mode equal to logical zero. The code of the number of the clock, given from the block 20 of the task, jg of the simulation mode, must be different from n5gl. The input 24 of the device is connected to the output of the hardware element, by a signal from which it is necessary to simulate a failure of a given duration. ,

When an external signal arrives at the start-up of the device, an sig5 is generated at the output of the element OR, which arrives at the counting input of the trigger 19 and switches it to the unit state. The trigger signal is also fed to the input element OR

. 9 which output is formed

The Q signal that sets the trigger 18 to the state O is enabled by the operation of the counter 4. By the signal from the output of the trigger 19, the switch 14 switches the co5 D fault duration to the second group of information inputs of the comparison unit 5. Further, the device works in the same way as in the first mode. After a failure in the equipment of a given duration, the circuit returns to its initial state.

In the third mode, the value of the single failure mode signal is 1. In this case, the counter does not zero after the end of the operation cycle of the device, since the trigger 18 is in the state O.

The operation of the device in each cycle of operation is similar to the operation in the first mode, except that no external signals are required to start the cycle of operation of the device. The device in this case generates a sequence of failures of a given duration, and the time interval (number of ticks) between adjacent faults is equal to the tick number code specified from the simulation task setting unit 20.

Claims (1)

Invention Formula A device for simulating failures of discrete hardware, containing a block for setting simulation modes, a comparison block, first switch, channel number decoder, counter, first element NOT, delay element, memory block, register, defect decoder, defect driver, AND element and first OR element The inputs of the first switch form the group of information outputs of the device, the group of information inputs of the device is connected to the first group of information inputs of the first switch, the second group of information inputs of The opus is connected to the group of outputs of the defect generator, the group of outputs for specifying the defect number of the block of the simulation mode is connected to the group of address inputs of the memory block, the group of outputs of which is connected to the group of information inputs of the register, the group of outputs of which is connected to the group of inputs of the decoder of the defect the outputs of which are connected to the inputs of the defect generator, the group of outputs for specifying the channel number of the block for specifying the simulation mode is connected to the group of inputs for the decoder of the channel number, the outputs of which are connected to the control inputs of the first switch, the output of the setback mode and the output of the setpoint mode 0 five 0 the failure of the simulation mode setting unit is connected to the first inputs of the AND element and the first OR element, the output of the AND element is connected to the second input of the first OR element, the output of which is connected to the gate inputs of the memory block and the channel number, the clock input of the device is connected to the synchronization input of the counter and with the input of the first element NOT, the output of the first element is NOT connected to the input of the comparison unit comparison resolution, the first group of information inputs of which are connected to the group of discharge outputs of the counter, differ In order to expand its functionality by changing the duration of the fault and controlling the inertia of the fault by external signals, the second switch, the OR-NOT element, two triggers, the second and the third elements, or the second element are introduced into it. NOT, and the group of outputs for setting the cycle number of the block for setting the simulation mode is connected to the first group of information inputs of the second switch, the second group of information inputs of which is connected to the group of outputs for setting the duration of the block for setting the simulation mode The output of the initial installation of which is connected to the input of the installation into 1 of the first trigger and with the input of the installation to 1 of the second trigger, the output of setting the single-time mode of the block of the simulation mode is connected to the first input of the second OR element, the second input of which is the first start input of the device , the output of the second element OR is connected to the input of the installation in O of the first trigger, the output of which is connected to the first input of the third element OR, the output of which is connected to the input of the delay element, the code of which is connected to the input set In the counter O, the comparison output of the comparison block is connected to the first input of the OR element and the second input of the third OR element, the second input of the OR element is NOT connected to the third input of the second OR element, and connected to the second start input of the device, the output of the OR element NOT connected to the counting input of the second trigger, the output of which is connected 0 five 0 five 0 five 114517028 with the counting input of the first trigger, the departure of the comparison unit, the output of the first with the second input of the AND element and the uploaded element OR is connected to the input by the equal input of the second switchboard of the second element NOT whose output, the group of outputs of which is connected with an entry zeroing with the second group of information register.