SU1536388A1 - Device for simulation of faults - Google Patents

Abstract

The invention relates to computing and can be used in the development of equipment and programs. The purpose of the invention is to extend the functionality of the device due to the possibility of simulating a series of failures. The device contains the first 1, second 2 and third 3 address registers, the first 4 and second 5 code registers, the first 6 and second 7 address counters, the simulated counter 8, the first 9 and second 10 comparison blocks, the address multiplexer 11 and the multiplexer 12 code trigger 13, one-shot 14, first, second, third blocks 15-17 of forming a fault signal, first to ninth elements AND 18-26, first 27 and second 28 elements OR, and switch 29. The device allows you to automatically set initial conditions for simulating failures in different channels and at different sites working out my programs are real time. 5 il.

Description

The invention relates to computing and can be used in the development of equipment and programs that monitor and diagnose faults in real-time.

The aim of the invention is to expand the functionality of the device due to the possibility of simulating a series of failures.

Figure 1 shows the functional diagram of the device; Fig. 2 is a functional block diagram of a malfunction signal; FIG. 3 is a functional diagram of an example implementation of an automatic fault setting block; 4 and 5 are timing diagrams explaining the operation of the device.

The device for imitation of faults (Fig. 1) contains the first 1, second 2 and third 3 address registers, the first 4 and second 5 code registers, the first 6 of the second 7 counters of the address, the counter of 8 simulations, the first 9 and swarm 30 comparison units, multiplexers addresses 11 and code 12, trigger 13, one-shot 14, the first - the third blocks 15-17 of forming a fault signal, the first - the tenth elements AND 18-26, the first 27 and second 28 elements OR, and the switch 29. The device also shows the first bus 30 addresses and the input 31 of the synchronization of the first bus address, the second bus 32 addresses and the synchronization input 33 of the second address bus, data bus 34, the device start input 35 and the output 36 of the device simulation end. In addition, the first 37, second 38, third 39, fourth 40 and fifth 41-43 output groups of the multiplexer 12 code are designated.

Each of the three blocks 15-17 forming a fault signal, for example, block 15 (FIG. 2), contains a 44 clock counter, a failure duration counter 45, a trigger 46, a first 47 and a second 48 OR elements, a first third element AND 49-51, and a driver 52 pulses, input 53 clock pulses.

The automatic fault setting unit 54 (FIG. 3) contains a memory unit 55 (ROM), a hodres register 56, an address counter 57, two pulses counter 58, a trigger 59. And 60,

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the element OR 61, the input 62 clock pulses and the input 63 start block 54.

Address registers 1 and code 4 are used to set the initial conditions in the manual configuration mode. In this mode, the initial conditions are set manually by the toggle switches before starting work. Address registers 2 and code 5 are designed to receive and store initial conditions in the automatic tuning mode, which come from the data bus 34. The address register 3 is designed to store a reference code corresponding to the address of the device in question on address bus 32 (several devices, for example, an instrumental mini-computer, memory blocks, input / output devices, etc.) can be found on the address bus.

The address counter 6 is designed to count the number of addresses that must be skipped before starting the fault simulation. Counter 7. Addresses are designed to count the number of addresses that must be skipped between fault simulations. Simulation counter 8 is designed to count the total number of faults at a given address in register 1 or register 2. Counters 6-8 can be implemented, for example, on standard IC 155IE7.

Comparison unit 9 is intended for comparing information on address bus 30 with information received from the outputs of address multiplexer 11. Comparison unit 10 is designed to compare information on the address bus 32 with a reference code specified on address register 3.

The address multiplexer 11 is designed to connect to the second group of inputs of the block 9 comparing the outputs of register 1 or register 2 depending on the position of the switch 29 (when connected to the common bus, the outputs of the multiplexer 11 receive information from the outputs of register 1, when the switch is open, from the outputs of the register 2, the open state of the switch is perceived by the multiplexer as in TTL logic - logical 1).

The multiplexer 12 code is designed to connect to its outputs the outputs of register 4 or register 5 in

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depending on the position of the switch 29 (when connected to the common bus, the outputs of the multiplexer 12 receive information from the outputs of the register 4; when the switch is open, from the outputs of the register 5

The outputs of the multiplexer 12 code are divided into five groups. The first group of outputs 37 sets a code to specify the number of addresses that need to be skipped before starting the fault simulation. In the second group of outputs 38, a code is set to set the number of cycles to skip before starting the fault simulation and the number of cycles corresponding to the duration of the fault signal. The third group of outputs 39 sets a code to specify the number of addresses that must be skipped between fault simulations. The fourth group of outputs 40 sets a code that sets the total number of faults. A position code is set on the fifth group of outputs 41-43, the unit value of each bit of which permits the triggering of the corresponding block 15-17 for generating a fault signal.

Multiplexers 11 and 12 can be implemented, for example, on standard integrated circuits 55KP11 Trigger 13 is designed to start the device and reset it after completing work on the given initial conditions. Single-oscillator 14 is designed to form a single pulse, strobe recording the initial conditions in the counters 6-8, 44 and 45. Single-oscillator 14 can be implemented, for example, on a standard integrated circuit 155AG1. Blocks 15-17 are designed to generate a fault signal after a predetermined number of clock cycles with a specified duration. Elements 18, 19, and 25 are designed to generate a start pulse that triggers blocks 15–17 to generate fault signals. Element And 20 is designed to form a write pulse in register 2 of the address information received from the data bus 34 with an even address on the bus 32 of the address and the higher bits match the reference code of register 3. Element And 21 is intended for

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generating a write pulse in register 5 of the information code received from data bus 34 with an odd address on the address bus 32 and the high order bits coincide with the reference register code 3. Element I 22 is designed to generate a pulse corresponding to the presence of the address 30 on the bus that needs to be executed imitation of malfunction. Element I 32 is designed to block the arrival of pulses at the counting i input of counter 6 after counting a specified number of addresses that need to be skipped before starting the fault simulation. Element And 24 is designed to block the arrival of pulses at the counting input of counter 7 and the first input of element And 26 until the specified number of addresses is read, which must be skipped before starting the fault simulation. Element And 26 is intended to 5 to form a pulse during the first simulation, as well as when counting the number of addresses that must be skipped between fault simulations. The OR element 27 is designed to generate a start signal for the device that sets the trigger 13 to be in one state. The element OR 28 is designed to generate a signal whose leading edge corresponds to the end of the next simulation of the malfunction.

The switch 29 is designed to set the operating mode of the device. When the contacts of the switch are closed, the mode of manual adjustment of the initial conditions is set. The open state of the switch sets the mode of automatic adjustment of the initial conditions that are received from the data bus 34 after all simulations are completed at the specified program address. The open state of the switch is perceived by multiplexers 11 and 12 as in TTL logic - logical 1H.

The counter 44 (FIG. 2) is designed to count the number of cycles that must be skipped before starting the fault simulation. The counter 45 is designed to count the number of clock cycles that corresponds to the duration of the malfunction simulation signal. Counters 44 and 45 can be implemented, on 0

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example, on standard chips 155IE7. The trigger 46 is designed to generate a start signal for the failure signal generation unit 15 after a pulse arrives at the trigger input; The element OR A7 is designed to form a recording signal in the information counters 44 and 45 received from the second group of 38 outputs of multiplexer 12. The element OR 48 is intended to generate a reset signal for trigger 46 | in the presence of a signal at the reset input lock 15 or by the presence of a signal at the output And 49. Element And 49 is designed to block the arrival of pulses at the counting input of counter 44 until the signal arrives at the start input of block 15 and after counting the number of cycles until the start of the fault simulation. Element I 50 is designed to block Pulses on the counting input of the counter 45 to the appearance of a single signal at the output of the counter 44 and the detection of a single signal at the output of the counter 45. Element I 51 is designed to generate a signal that controls the driver 52 of the malfunction. Shaper 52 is designed to generate a fault signal that is consistent with the parameters corresponding to the requirements of the equipment being processed. Shaper 52, when issuing a malfunction signal on the line of the computer being processed, can be implemented, for example, on standard open-collector microcircuits (155LA7), or microcircuits with three output states (589АП16).

Block 54 auto set | Failures are designed to organize real-time simulations of failures or failures in different parts of the program being worked out and (or) in different channels of the equipment being worked out by automatically setting new initial conditions after completing the next simulation upon arrival of an impulse from the output 36 of the device imitations.

As a unit 54, an instrumental or technological computer can be used (either standard mini or microcomputer); may be

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A directly processed computer is used (in this case, address buses 32, 33 and 30, 31 are combined into one bus, and the automatic setting of initial conditions is carried out via a debugging program, which is controlled by interruption after the output from the output 36 of the simulations is issued). Using an instrumental computer or a debugging program makes it easy to carry out a variety of faults when working in real time. In addition, the automatic setting unit 54 can be implemented as a special device shown in FIG.

The memory unit 55 is designed to store the values of the initial conditions. The even addresses of the block 55 store the addresses where the malfunction is simulated; the odd ones contain codes that specify the number of address skips before the simulation, the number of cycles before the simulation, the number of cycles corresponding to the simulation duration, the number of address gaps between simulations, the total number imitations and channels in which imitations are required.

The memory unit 55 may be implemented, for example, on standard chips 155REZ. The address register 56 is intended to store the upper order bits of the address to which the proposed device is configured (FIG. 1). The address counter 57 is designed to iterate through the addresses of the memory unit 55, from which output to the data bus 34, initial conditions are set to simulate malfunctions. Counter 58 is designed to count two pulses at the output of element AND 60, which gates the output from block 54 through bus 34 of two information words containing initial conditions. Counters 57 and 58 can be implemented on 1K-triggers, for example, on standard chips 155TBJ. The trigger 59 is designed to start block 54 and stop it after issuing two information words to the data bus 34. Element I 60 is designed to block the arrival of clock pulses while waiting for a start pulse at input 63 or a pulse at output 36 of the end of device simulations.

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The element OR 61 is designed to form a signal by setting the trigger 59 in one state upon the arrival of a pulse to the input 63 or a pulse to the output 36 of the end of simulations.

Device for simulating faults works as follows.

In the initial state, the trigger 13 is in the zero state (the installation chains to the initial state of the trigger 13 are not shown). A single signal from the inverse output of the flip-flop 13 is fed to the fault inputs of counters 6-8, 44 and 45 and flip-flop 46, as a result of which they are in the initial zero state.

The device can operate in two modes: the mode of manual setting of initial conditions and the mode of automatic setting of initial conditions, which come from the data bus 34 after all simulations are completed at a given address of the program being processed.

Consider the operation of the device in the manual setting of initial conditions. In this mode, the contacts of the switch 29 are closed and the control inputs of multiplexers 11 and 12 receive a zero signal allowing information to pass to the outputs of multiplexers 11 and 12 from the outputs of address registers 1 and code 4. At address register 1 is set

address of the program being worked out, on which it is required to perform imitation of faults. On register 4 of the code, an information word is set specifying the initial conditions. The format of the information word contains five fields. The first field contains a code that specifies the number of addresses that must be skipped before starting the simulation of faults. The second field contains the code specifying the number of cycles that must be skipped before the start of the fault simulation, as well as the number of cycles corresponding to the duration of the fault signal. The third field contains a code specifying the number of addresses that must be passed between fault simulations. The fourth field contains the code that sets the total number of imitations of faults. The fifth field contains the position code, the unit value of each bit of which

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Allows the triggering of the corresponding block 15-17 forming a fault signal.

After setting the registers 1 and 4 of the necessary initial conditions to simulate faults, a single pulse is applied to the device start-up input 35, which, having passed through the OR element 27, sets trigger 13 into one state, as a result of which the signal from the reset inputs of counters 6-8 is removed , 44 and 45, and trigger 46. A single signal from the output of the trigger 13 is fed to the input of the one-shot 14, resulting in the output of the one-shot 14 L-normalized single pulse to the write inputs of the counters 6 and 8 and blocks 15-17 of equality. The same signal in blocks 15-17 through the element OR 47 is fed to the write inputs of counters 44 and 45. On the falling edge of the pulse at the output of the one-vibrator 14, the contents of the first, second and fourth fields of the register 4 code through multiplexer 12 are copied to the first counter 6 of the address, counters 44 cycles and the duration of the failure of 45 blocks 15-17 and 8 counter imitations.

After recording the initial conditions in the counter 6-8, 44 and 45 device

ready to go. The first group of inputs of the comparison block 9 with the first bus 30 addresses receives the address values of the program being processed. The second group of inputs of the comparison unit 9 from the outputs of register 1 of address, through multiplexer 11, receives the value of the program address, at which it is required to perform a fault simulation. When the address on bus 30 coincides with the contents of address register 1 and there is a gate clock at input 31 of the first bus 30 address, output impulse I 22 generates a pulse coming through element 23 (open inverse) to the counting input of address counter 6.

If you need to skip before performing a fault simulation

the specified number of cycles of the program being processed, then the counter 6 contains the corresponding setpoint, and a single signal at its output

After counting the required number (mastering the addresses on the bus 30 addresses

If imitation is required to be performed at the first match of the addresses, then in Counter 6 a zero code is entered and, by the First Pulse, at its counting input at the output of counter 6, Vits |: overflow signal. A single signal at the output of the counter 6 of the address prohibits the further arrival of the counting input of pulses through the AND 23 element to the go and allows the passage of pulses through the AND 24 element to the counting input of the second counter 7 and the element 26. The counter 7 is in the zero state and when the unit is subtracted by the leading edge of the pulse arriving at its counting input, at output 7, appears a single overflow signal, which flows through AND 26 to the inputs of AND elements

8, 19 and 25. Depending on the code of the initial conditions in the fifth field of the information word stored on register 4, elements 18, 19 and 25 allow or prohibit the passage of the signal to the start inputs of blocks 15–17 of the normalization of the malfunction signal, 17 forming an inaccuracy signal, to the start input of which a pulse arrives, through a given Number of ticks, a Fault signal is generated at the corresponding information output with a given Duration, Number of ticks before the start of simulation and the number of Tacts corresponding to The fault signals are set as initial conditions in the second field of the information word stored in register 4.

At the end of the issuance of the signal. Faults from the outputs. The end of the simulation of blocks 15-17 is given a signal, which through the element OR 28 goes to the counting input of the counter 8 simulations. If one simulation is required, then when setting the initial conditions, a zero code is written to it. On the leading edge of the signal at the counting output of the counter 8, a single overflow signal appears at its output, which is fed to the R input of the trigger 13 and to the output 36 of the end of simulations. As a result of resetting the flip-flop 13, a signal appears at its inverse output, which resets the device to its initial state. .

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If it is necessary to perform several simulations, then in the counter 8 simulations, when setting the initial conditions, a number one less than the required number of simulations is entered. If it is necessary to perform several simulations at a given address with the omission of a certain number of program cycles, then a counter equal to the required number of program cycles to be entered is entered into counter 7 when setting the initial conditions. In this case, the falling edge of the pulse at the output of the AND 26 element into counter 7 rewrites the code from the output 39 of the multiplexer 12, as a result of which a single overflow signal is removed from the output of the counter 7 and the passage of pulses through the element 26 to the next overflow of the counter 7 is prohibited.

The malfunction signaling unit, for example, block 15, operates as follows.

In the initial state, the signal from the fault input of the unit 15 triggers 46 and the counters 44 and 45 are set to the zero state. On the falling edge of the pulse arriving at the input of the block entry, counters 44 and 45 rewrite the initial conditions from the information inputs, which are divided into two groups. On the first group of inputs, a code is set to write to counter 44, on the second group to write to counter 45. A pulse arriving at the S input of the trigger 46 sets it to one state, thereby deciding the passage of clock pulses through AND 49 44 counts to the counting input of the counter, which counts the number of cycles required before the start of the alarm simulation signal. Upon overflow of the counter 44, a single signal appears at its output, coming through the open element AND 51 to the input of the malfunctioning signal generator 52. The same signal permits the passage of clock pulses to the counting input of the failure duration counter 45, which counts the number of clock cycles corresponding to the time of the malfunction signal simulation. By overflowing the counter 45, a single signal appears at its output, which closes the AND 51 element, thereby ifpe-

Giving a Simulated Fault Signal The same signal closes the AND 50 element, stopping the arrival of clock pulses at the counting input of counter 45, and the signal Simulation End is output to the input of block 15. On the falling edge of the signal at the output of the And 51 element, the counters 44 and 45 rewrite the initial conditions, after which the block 15 is ready to form the next malfunction signal. In the automatic setting of the initial conditions, the device works similarly, the difference is that the setting and the initial conditions occur by the initial conditions from the data bus 34 are written to the address register 2 and the code register 5, and in this mode the contacts of the switch 29 are open, which corresponds to a single signal at the control inputs of the multiplexers, due to Which information from the outputs of registers 2 and 5 goes to the outputs, multiplexes 11 and 12. The recording of the initial conditions in registers 2 and 5 occurs as follows. The device on the second bus 32 addresses has two adjacent addresses, even and odd. Register 2 addresses correspond to an even address, register 5 code - an odd address. The recording of the initial conditions begins with the addressing of the device at the even address. If there is an even address on bus 32 and the block of 10 high-order address bits is compared with the reference code of register 3 of address, a signal appears at the input 33 of the address at the output of the AND 20 element. A pulse appears on the leading edge of which address 2 is written to register 2. which requires a simulated malfunction.

Next, on bus 32, an odd device address is set, and when recognizing the output of element 21, a pulse appears, on the leading front of which an information word containing initial conditions is recorded in register 5. The same pulse through the element OR 27 is fed to the S-input of the trigger 13, as a result of which the device starts to work in the same way as the rune-tuning mode described. Upon completion of a predetermined number of simulations, at the output 36 of the end of simulations an impulse is formed, signifying readiness

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devices for receiving successive initial conditions.

The automatic fault setting unit 54 operates as follows.

In the initial state, the counter 57 of the address, the counter 58 and the trigger 59 are set to the zero state (the reset circuits are not shown). Block 54 starts when a single pulse arrives at input 63, through which trigger 59 is set to one, thereby enabling the arrival of clock pulses at the counting inputs of counters 57 and 58 and address synchronization output 33. On the leading edge of the first clock pulse, content is stored from memory block 55 stored at the zero address on the bus 34 of data. On the trailing edge of the clock pulse, the contents of the counter 57 of the address and the counter 58 increase;

On the leading edge of the second clock pulse from the memory unit 55, the data stored at the first address is output onto the data bus 34. On the trailing edge of the second clock pulse, the contents of the address counter 57 increase, and a single signal appears at the output of the counter 58, which resets the flip-flop 59, followed by. The element 60 is closed, the counter is reset. 58. and block 54 goes into waiting for a pulse at input 36, which starts block 59 to output the next two information words to the data bus.

Claims (1)

Invention Formula A device for simulating faults, containing the first and second address registers, the first and second code registers, the address counter, the first and second malfunction signaling blocks, the trigger, the first and second comparison blocks, the first and second elements, And the first device address bus connected to the first group of inputs of the first comparison unit; the outputs of the first and second elements And, respectively, are connected to the start inputs of the first and second failure signal generation blocks,. the outputs of which are the first and the second information outputs of the device, characterized by that, in order to expand the functional capabilities of the device due to the possibility of simulating a series of failures, a third address register, an address multiplexer, a code multiplexer, a second address counter, a simulation counter, a third generation unit, a fault signal, a single vibrator, two elements OR, seven AND elements and a switch, the output group of the third address register is connected to the first group of inputs of the second comparison unit, the second group of inputs of which is connected to the second device address bus, and the output is connected to V The third inputs of the third and fourth And elements, the first inputs of which are connected to the synchronization input of the second device address bus, the lower order bits of the device address bus are connected to the inverse input of the third And element and to the third input of the fourth And element, the outputs of the third and fourth And elements respectively, with the recording entries of the second address register and the second code register, the groups of information inputs of which are connected to the device data bus, the outputs of the first and second address registers, respectively, are connected with the first and second groups of information inputs of the address multiplexer, the outputs of which are connected to the second group of inputs of the first comparison unit, the output of which is connected to the first input of the fifth And element, the second input of which is connected to the synchronization input of the first device address bus, and the output of the fifth And element connected to the first inputs of the sixth and seventh elements And, the clock inputs of the blocks forming the fault signal connected to the clock input of the device, the starting ACHD device and the output of the fourth element And through the first The OR input is connected to the S-input of the trigger, the direct output of which is connected to the one-shot input, and the inverse output is connected to the fault inputs of the first and second address counters, the simulation counter and the fault inputs of the three malfunction signaling blocks; an address counter, an imitation counter, and a malfunction signaling unit; 0 five 0 five 0 five ABOUT five 0 five The control inputs of the address and code multiplexers are connected to a movable contact of the switch, the fixed contact of which is connected to the device zero-potency bus, the outputs of the first and second code registers are connected respectively to the first and second groups of information inputs of the multiplexer code, the first to fourth groups of outputs of which are connected respectively to the group of information inputs of the first address counter, groups of information inputs of the malfunction signaling blocks, a group of information in the moves of the second address counter and a group of information inputs of the counter of simulations, the fifth group of outputs of the multiplexer code is connected to the first inputs of the first, second and eighth elements I, the output of the sixth element I connected to the counting input of the first counter of the address, the output of which is connected to the inverse input of the sixth element I and the second input of the seventh element And, the output of which is connected to the first input of the ninth element And, and with the counting input of the second counter of the address, the output of which is connected to the second input of the ninth element And, the output which is connected to the input of the record of the second address counter and the second inputs of the first, second and eighth elements AND, the output of the eighth element AND is connected to the start input of the third signal generation unit, the output of which is the third information output of the device, the outputs of the simulation of three formation units the fault signal through the second OR element is connected to the counting input of the simulation counter, the output of which is the output of the end of the simulation of the device and is connected to the R input of the trigger, each block forming the fault signal contains the first, second and third elements AND, the first and second elements OR, the clock counter, the failure duration counter, the trigger and the pulse shaper, the start input of the malfunction signaling unit connected to the S-trigger inputs, the R-input of which is connected to the output of the first element OR, and the output - with the first input of the first element AND, the input entry block 1715 The fault signal is connected to the first input of the second OR element, the output of which is connected to the inputs of the clock counter and the failure duration counter, whose information input groups are connected to the information input groups of the malfunction signal generation unit, the fault input of which is connected to the first input of the first OR element, the fault inputs of the failure duration counter and the cycle counter, the output of which is connected to the first input of the second element I, with the inverse input of the first element I and C The first input of the third element And the input of the clock pulses of the block 18 generating a malfunction signal is connected to the second inputs of the first and second elements I, the outputs of which are respectively connected to the counting inputs of the tact counter and the failure duration counter, the output of the failure duration counter is the output of the simulation of the malfunction signal generation unit and connected to the inverse inputs of the second and third elements , the output of the third element AND is connected to the second inputs of the first and second elements OR, and to the input of the pulse former, the output of which is informational in stroke unit. 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