SU1647518A1 - Programmable logical controller - Google Patents

Abstract

The invention relates to devices for program-logic control of discrete-cyclic objects and can be used as an ACS controller for technological processes. The purpose of the invention is to increase speed and reduce hardware costs. The purpose of the invention is achieved by the introduction of registers, the third AND element, the OR element, the trigger, the delay element. The essence of the invention is to increase speed by providing direct access to the address of the first command, the ability to memorize the code of the address of the command where the main program was interrupted, then return to it, and also to reduce the hardware costs by reducing the memory size and simplifying control the passage of signals. 5 il „a ss (L

Description

The invention relates to devices for software and logic comparing of objects of discrete-cyclic action and can be used as an ACS controller for technological processes.

The aim of the invention is to improve the speed of the device and reduce hardware costs.

The essence of the invention is to improve the speed of the device based on providing direct access to the address of the first command and the ability to memorize the code of the address of the command where the main program was interrupted.

 with subsequent return to it Reduced hardware costs due to a decrease in memory; simplifying the control of signal flow,

Fig 1 is a functional diagram of a programmable logic controller; on Lig0 2-4 - time diagrams Functioning of the programmable logic controller when working on the main subroutine, working on the main subroutine, with interruption and when oj-processing the main subroutine with interruption and memorization; in fig. 5 - timing diagram of the synchronization of the programmable logic device.

Programmable logic controller (Fig. 1) contains block 1

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comparison, blocks 2-4 of memory of combinations of states, on and off commands and addresses of transitions, respectively, generator 5 clock pulses, first counter 6 pulses, first 7, second 8 and third 9 elements AND "element OR 10, delay element 11, register 12.1 address codes and sensor status register 12.2, switch 13, trigger 14 and display unit 15 In FIG. 1, outputs 4.1-4.3, 5.1-5.2 and 3.1-3.2 are marked respectively blocks 4, 5 and 3.

Comparison unit 1 is designed to compare the sequence of state combinations9 into which the sensors fixing the position of the mechanisms as a result of executing the corresponding commands, and the actual sequence of state combinations that the sensors have passed as a result of executing the corresponding command, and issuing on the basis of this comparison signal for the transition to the next microcommand of the subprogram “

The memory unit 2 is used to store a sequence of combinations of states to which the sensors must go, fixing the position of the mechanisms as a result of the execution of the corresponding commands. Memory block 3 is designed to record a sequence of combinations of commands for switching on and off mechanisms. In all lines of the block, one bit is allocated to program the end of the subroutine (R),

Memory block 4 is used to record the addresses of the jumps to the new subroutine in the program as a result of working out the next subroutine or, if necessary, moving to the emergency subroutine. In all lines of memory block 4, one bit is allocated for programming the sign of storing the microprogram address, which interrupted the testing of the subroutine as a result of testing the next step, which does not contain the sign of interruption "

The sync pulse generator 5 is used to generate and output pulses of positive polarity in order to synchronize the operation of the entire controller (Figs 5). The counter 6 clock pulses is intended for storing and issuing address information

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microcommands contained in the first 2 and second memory blocks; The first element And 7 is designed to form a signal that switches the counter 6 pulses into the next state (n + 1). The second element And 8 and the delay element 11 are used to form a signal that zeroes trigger 14 "The third element AND 9 and the element OR 10 are used to control the mode of operation of the device

Register 12.1 is intended for receiving, storing and issuing an address code of a micro-command that interrupted the main sub-program of an emergency. Moreover, the information is recorded in the register 12.1 by the sync pulse при {if there is a high potential at the inputs V ,,. Register 12.2 is intended for storing injecture about the state of the sensors. Recording information occurs on the clock pulse V. This ensures stable operation of the device.

Switch 13 is used to provide the recording of information about the address of the first microcommand of the subroutine to the pulse counter from register 12 or memory block 4. The trigger 14 is used to control the passage of information through the switch 13,

The display unit 15 is designed to display information used to diagnose faults: the line number of the subroutine on which it stopped (from the output of the pulse counter b), the status of the controller inputs and outputs, and from the first output of the comparison unit 1 the information about the sensors is output. - which state does not match the programmed one. Both state sensors and control and protection controls, informational and electrical interlocking signals from other devices can be used as state sensors and state transition sensors. For example, programmable stationary memory blocks can be used as memory blocks. data storage devices of various types.

The principle of operation of the programmable logic controller is as follows.

The installation of a programmable logic controller to the initial connection is carried out using an external pulse signal of the initial installation (the initial installation circuit in Fig. 1 is not shown) and consists in resetting the counter 6. The processing of the control program consists of analyzing the combinations of the transition condition sensor states (states of the external environment) and the formation of the initial address of the subprogram, the actual processing of the selected subprogram, the analysis of the state of the external environment is carried out in parallel and independently from working out the subroutine.

When the initial setup signal is applied, the counter 6 is zeroed. In this case, from the first output of the memory block 3 to the controlling object, the control commands are written in the line with the address corresponding to the output of the counter 6, in this case zero, the corresponding mechanisms are triggered, and therefore the sensors, i.e. the first command of the first subroutine is executed. The resulting combination of the actual states of the cycle sensors is compared using a comparison block with a combination of states read from memory block 2 at the same address. When the actual combination of conditions coincides with the programmed and no signals at output 3.2 of memory block 3 and output 4 22 of memory 4, the match signal of the compared combinations from the output of comparison unit 1 opens element 7 and a pulse from output 5-1 of the generator 5 sync pulses switches the counter 6 to the next state, that is, the next subprogram command is called.

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Unit 6 of the new address switches blocks 2 and 3 of the memory, and the signal from output 3.2 of the block & 3 memories. Therefore, the AND 9 element is closed, and the first AND 7 element is opened. Further operation of the controller is similar until the controlled object enters an emergency state.

This state is fixed by the memory block 4, and an interrupt signal (Pr) appears at the output 402 of the memory block 4, and the address of the subroutine that must be implemented to output the controlled object from the alarm state at the output 4 01. In such a situation, in unit 1 of the comparison, the actual state of the sensors does not compare with the programmed one, i0. there is no signal at the output of comparison unit 1. The high potential of the signal Pr from the output of the element OR 10 closes the element AND 7 and opens the element AND 8 to pass the next sync pulse to the clock input of counter 6. This synchronization signal records the address of the alarm subroutine into the counter 6. Further processing of the subroutine is similar.

Some differences in the operation of the circuit exist during the transition and testing of the emergency subroutine if it is necessary to memorize the address of the line on which the main subroutine is interrupted. The need to memorize the address of the line being processed is shown by the output 4.3 of memory 4. This signal appears simultaneously with the interrupt signal. In this case, the interrupt signal passes through the element OR 10, closes the element AND 7 and opens

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This process continues until the input element 9 and the memory signal

laziness at output 3.2 of block 3 of memory of a single signal. End of subroutine. When this signal appears, element 7 is blocked by a high potential from the output of element OR H and the same signal allows the signal through element 9 to pass to the synchronous input of counter 6. This signal records the address of the next command of memory 4 through switch 13. Address The new command is contained in block 4 of memory in the line with the address corresponding to the current state of the sensors. When writing to the account

The recording of information in reg. 12.1 is avoided. The next clock signal from the output and the generator 5 clock pulses - front edge records

50 information from the output of the counter 6 into the register 12 12 1 and from the output 401 of the 4-mi block through the switch 13 to the counter and the falling edge switches trigger 14 to one state. Wherein

55 from the output 3 "1 of the block 3 of the memory to the controllable object — the subprograms of the control panel written on this line are output. The sensors go to the next state

Record information in the register 12.1. The following clock signal from the output of the 5 sync pulse-front edge records

information from the output of counter 6 to register 12 and 1 and from output 401 of memory 4 through the switch 13 to counter 6, and the falling edge switches trigger 14 to one state. Wherein

output 3 "1 of block 3 of memory to the controlled object - control commands written on this line are output. Sensors go to the next state

In connection with this, the AND 9 element is closed, and the AND 7 element skips the next clock pulse to the counting input of the counter b, t, e, the next line of the memory blocks 2 and 3 is accessed. This process continues until the end of the subroutine appears. Element 7 is closed by this signal and element And 9o is opened. The next clock pulse, passage through the third element 9, allows the information to be recorded into counter 6 from the output of register 12 "f". Thus, the return to the subroutine line by which the interrupt occurred, and at the same time the trigger 14 switches to the zero state, i.e.

The counter 6 input is connected to the output of memory block 4. Subsequently, the subroutine continues to be processed in a similar way.

If at any step of the subroutine there is a failure or breakdown of the mechanism or sensor (but not leading to an emergency situation), the transition to the next line of the subroutine does not occur (since the comparison unit .1 cannot compare), and The display unit 15 displays information used to diagnose faults: the line number of the subroutine at which the stop occurred (from the output of counter 6), the states of the inputs and outputs of the controller. After elimination of the revealed malfunction the device continues working out of subroutines

The technical and economic advantage of the proposed controller over the known one is to increase the speed by providing direct access to the address of the first command of the new subroutine stored in the memory unit, as well as the ability to programmatically store the address of the line on which the main programs, and a decrease in hardware costs, due to a decrease in the memory size and simplified control of the passage of the signal

Claims (1)

Invention Formula A programmable logic controller containing a memory block of state combinations, a memory block ten five 0 50 five 0 switching on and off and a block of memory of addresses of transitions, the first pulse counter, the first and second elements And, a clock generator, a comparison unit, a switch and a display unit, the first input of the display unit connected to the output of the state combinations memory block, output: pulse counter connected to the address inputs of the combinations of the memory of the combinations of the states and the memory of the on / off commands, the second input of the display unit is connected to the output of the comparison unit, the third input is connected to the information output of the counter pulse , the fourth input - with the information output of the on / off command memory and the output of the programmable logic controller; the second output of the comparison unit is connected to the first input of the first And element, the second input of which is connected to the output of the clock generator, the output of the first And element is connected to the counting the input of the pulse counter, the second output of the on / off command memory block is connected to the first input of the second AND element, characterized in that, in order to increase speed and decrease hardware waste, it contains the register of the address code and the sensor state register, the third AND element, the OR element, the trigger, the delay element, the information input of the address code register is connected to the output of the pulse counter, the first input of the OR element is connected to the first output of the address memory block transition, -, the second input is connected to the second output of the memory of the on / off command commands, the code of the OR element is connected to the third input of the first element . 45 and the second input of the second element AND 0 five connected to the output of the third element And, the output of the second element And through the delay element connected to the zero input of the trigger, the output of the element OR is connected to the first input of the third element And, the second input of which is connected to the first output of the clock generator, the output of the third element And is connected to the synchronous input of the pulse counter , the synchronous input of the code of the address of the register and the trigger is connected to the first output of the pulse generator t the second output of the memory block of the address of the transition c, is connected to the control 916 V is the input of the address code register and with a single trigger input, the inverse output of which is connected to the control Vj input of the first address code register, the output of which is connected to the first information input of the switch, the second information input of which is connected to the third memory address address block, The first control input is connected to the second output of the memory module of the command r on and off, the second control input is connected to the direct gtzg 52 ten 122 Pi 1-3 sh eight eleven YU the trigger output, the third control input to the output of the OR element, the switch output is connected to the information input of the pulse counter, the second clock generator output is connected to the synchronous input of the sensor status register, the information input of which is the controller input, the sensor status of the register is connected to the second the information input of the comparison unit, to the address input of the memory of the transition address and the second input of the display unit. +1 J 1S but Sz VI V1 С 121 itj : 3 & irrq PEN 1 6S, fl П П