SU1261014A1 - Device for checking blocks of internal memory - Google Patents

Abstract

The invention relates to computing and is intended for the control of memory blocks. The aim of the invention is to increase the reliability of the device. The device contains a pulse generator, a driver of the reference signals, counters from the first to the fifth, switches, a comparison unit and a control unit that sets the control programs with the tests "Running O and 1 or" Running 1 and O. The device allows you to control as memory cells, both BIS memory, and the sampling time of each BIS memory, for which the fourth and fifth counters, which form the memory BIS address, and the second switchboard are entered into the device. 2 Il. Ic o

Description

The invention relates to a computing technique and is intended for controlling RAM blocks.

The aim of the invention is to control the reliability of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional block diagram of the control unit.

The device contains (Fig. 1) generator

1 impulses, control unit 2, shaper 3 reference signals, counters 4 --8 first to fifth, comparison block 9, first 10 and second 11 switches. FIG. 1 shows a controlled memory unit 12 with the decoder 13 and the LSI 14 memory included in it.

FIG. 1 shows the initial installation input 15, the start input 16, the device stop input 17, the generator output 18, the outputs 19 and 20, the input 21, the outputs 22-24, the input 25, the output 26, the input 27, the output 28, the input 29, the output 30, input 31, output 32, inputs 33 and 34 of control unit 2, informational 35, address 36 and 37 device outputs, informational inputs 38 of the device, outputs 39 and 40 of the unit

2 controls, outputs 41-44 counters 1, 5, 7, and 8, respectively.

Control unit 2 contains (Fig. 2) triggers 45 and 46, element 47, e.; 1 indication 48, microprogrammed automaton (MPA) 49, driver 50 of impulse control signals, element OR-NOT 5, generator 52 of the signal for performing a transition condition . FIG. 2 also shows the inverse and direct outputs of the trigger 45. the direct output of the trigger 46, the input of the MPA 49. the input of the display element 48, the outputs of the control signals of the MPA 49, the outputs of the signals of the transition conditions of the MPA 49, the input of the signal of the fulfillment of the condition of the transition of the MPA 49. 9 comparisons include LEDs to indicate the results of the comparison.

The device works as follows.

The device is installed in the initial state by the initial installation signal at input 15, which zeroes the counters 4-8, and also sets all triggers of block 2 to zero, forma- tions of body 3 and block 9. To start the device input 16 sends a start signal, and it starts to generate signals that control the memory block of the test. “Running O and 1, and“ Running 1 and O. ”Thus, in recording mode, in block 2, the resolution signals are generated samples and records, respectively, entering iia input 22 (the selection enable signal pki) and to input 23 (write-read signal). Oi) p- world-meter 3 in this mode produces a background Φ (equal to O or 1) or a test T number (equal to 1 or 0), which arrives

to inputs 35 of block 12. Choice of background Φ or test 7 number () of suicity;: according to the signal at input I, which is located on the driver 3 L of the output oj OKa 2. The address of the GE in BIS 14 is fixed by a counter 4 or 5.

 from the terminal 4 and 5 through the switch 10 is fed to the inputs 36, i.e. lia address inputs BIS i4. The selection of the address code from counter 5 or counter 4 is performed by sigal.m. and output 40. The address of the LSI

14 in block 12 is formed by a counter 7 or 8 and through the switch 11 enters the inputs of the decoder 13. The selection of the address code from counter 7 or 8 is also performed by the signal at the output UJ. The enable signal of the sample from output 22 suggests the inputs of switches 10 and 11. The address code in counter 6 is always changed so that it is equal to the difference between the address codes at the outputs of counters 4 and 5 or the difference between the address codes at the outputs of counters 7 and 8, i.e. . in the counter 6 tracks the execution of the unit.uvi (sipgal at the output 33 of HJiH at the output 34) of the device from one state to another (for example, from the read state zero - fop-1U1 o number - to the cocTOHHiic readout of the test number equal to 1 ). The change of the address code in all counters 4--8 is carried out by the imp. 1c signals at inputs 24, 26, 28, 30, 32. In read mode, block 2 generates a sample enable signal at output 22 and read signal at output 23,

In this mode, the shaper 3 generates a reference point F or a test T number, which goes to the inputs of block 9, to the other inputs of KOTOpoi O from the outputs 38 of block 12, the read numbers arrive: 1o. On the control unit;;: shy input of block 9 and exits from output 39

CI, |), which compares the standard ({no-io and is read from numbers). The comparison results are indicated by elements of the indication (9.). The address of the GE in the BI (14 and the address of the BIS 14 itself is formed in this mode). ,

as described by you.kl ll | 1e.; kim records. The synchronization operation of the device is performed with clock pulses from the output 18 of generator 1. To stop the device

Rohomili isoreoreteni

The Stigia SEW, ()., (By comparison, counters with uepBorcj iO t) and switchboard. ; |) what is the location of the input | of the reference signal generator and counters, the first inputs of the control unit and the comparison unit in the section of the input of the input. the device, the input — whether the cell and the ocTaiioua cat — are the second and third inputs b;: eye up-: avlen1, and quarters (1 Kcropojo 1; e) dcl) to the output of the pulse generator and the second inputs of the comparison unit and shaper reference signals, the inputs from the third to the ny and the first output of which are connected respectively to the outputs from the first to the third and fifth input of the control unit, the outputs from the fourth to the sixth and inputs from the sixth to the eighth of which are connected to the counting inputs and to one of outputs of counters from the first to the third drush. IMI the outputs of which are the third and ninth outputs of the control unit, the outputs of the first switch are one of the address outputs of the device, characterized in that, in order to increase the reliability of the device, the second switch, the fourth and fifth counters, one of the outputs of which are connected to the inputs of the second switch, the first and second control inputs of which are connected to the third

These outputs of the first and second counters are co-0 and the seventh outputs of the control unit, are divided into inputs of the first switch, the first and second control, whose inputs are connected to the third and seventh outputs of the control unit, the eighth output of which is connected to the third input of the comparison unit The inputs of the first group of which are connected to the outputs of the generator of reference signals, the inputs of the second group of the comparator unit and the outputs of the generator of reference signals are the information inputs and outputs of the device, controlled and eleven the fifth outputs of which are connected respectively to the counting inputs of the fourth and fifth counters, the other outputs of which are connected to the ninth and ten - |, second inputs of the control unit, the eleventh input of which is connected to another output of the third counter, the installation inputs of the fourth and fifth counters are connected to the first input of the control unit, the outputs of the second switch are the other address outputs of the device.

The III outputs of which are the third and ninth outputs of the control unit, the outputs of the first switch are one of the address outputs of the device, characterized in that, in order to increase the reliability of the device, the second switch, the fourth and fifth counters, one from the outputs of which are connected to the inputs of the second switch, the first and second control inputs of which are connected to the third

and the seventh outputs of the control unit,

The four and ten outputs of which are connected respectively to the counting inputs of the fourth and fifth counters, the other outputs of which are connected to the ninth and tenth inputs of the control unit, the eleventh input of which is connected to another output of the third counter, the installation inputs of the fourth and fifth counters are connected With the first input of the control unit, the outputs of the second switch are different address outputs of the device.

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Claims (1)

Claim A device for monitoring random access memory blocks, comprising a control unit, a pulse generator, a reference signal generator, a comparison unit, counters from the first but third and first switches, the installation inputs of the reference signal generator being counters, the first inputs of the control unit and the comparison unit being an input /! New installations of the device, the start and stop inputs of which are the second and third inputs of the control unit, the fourth input is connected to the output of the pulse generator and the second inputs of the unit comparison and a shaper of reference signals, the inputs from the third to fifth and first outputs of which are connected respectively to the outputs from the first to third and fifth inputs of the control unit, the outputs from fourth to sixth and inputs from the sixth to eighth of which are connected respectively to the counting inputs and to one of the outputs of the counters from first to third; the other outputs of the first and second counters are connected to the inputs of the first switch, the first and second control inputs of which are connected to the third and seventh outputs of the control unit, the eighth in the path of which is connected to the third input of the comparison unit, the inputs of the first group of which are connected to the outputs of the reference signal generator, the inputs of the second group of the comparison unit and the outputs of the reference signal generator are information inputs and outputs of the device, the control outputs of which are the third and ninth outputs of the control unit, outputs the first switch is one of the addressable vyhodo device, characterized in that, in order to increase the reliability of the device ^5, it introduced a second switch, the four the fifth and fifth counters, one of the outputs of which are connected to the inputs of the second switch, the first and second control inputs of which are connected to the third 10 and seventh outputs of the control unit, the tenth and eleventh outputs of which are connected respectively to the counting inputs of the fourth and fifth counters, the other outputs of which are connected with the ninth and tenth _5th inputs of the control unit, the eleventh input of which is connected to another output of the third counter, the installation inputs of the fourth and fifth counters are connected to the first input of the control unit The outputs of the second switch are the other address outputs of the device. Fig. 1 φυζ.Ζ.