SU1242918A1 - Device for diagnostic checking of control systems - Google Patents

Abstract

The invention relates to automation and instrumentation technology and can be applied in the diagnosis of control systems. The introduction of a third block of semi-permanent memory, a second register, a bit switch, a generator of logical zero, a generator of a logical unit, a shift register, a third register, a third decoder, a third switching unit and the fourth decoder increase the speed of the device, t. e. to shorten the time of troubleshooting of the diagnosed unit, since no accumulations of deviations of the diagnostic test are performed with subsequent testing, and as they are received, the interpretation of dependency dependencies is performed immediately. The device contains a pulse generator, first, second and third pulse counters, first, second and third switching blocks, first, second and third registers, first, second and third decoders, first, second and third blocks of semi-permanent memory, encoder, analog digital converter, first, second, third, fourth, fifth and sixth switches, first and second comparison blocks, first and second OR elements, first and second RAM blocks, logical zero and logical unit generators, bit switch, p giste shift display unit. 1 il. about b W 1C 4ii tc CO

Description

The invention relates to automation and test equipment and can be applied in the diagnosis of control systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows the functional diagram of the device.

The device has a generator of 1 pulses, the first counter of 2 pulses

 "T"

second counter 3 pulses. the first

switching unit 4, first register 5, first decoder 6, second semi-permanent memory unit 7, encoder 8, diagnostic unit 9, analog-to-digital converter 10, first switch 11, third switch 12, first element 1shir 13, second switch 14, the second element OR 15, the first and second blocks 16 and 17 of the RAM, the fourth and fifth switches 18 and 19, the second decoder 20, the sixth switch 21, the first comparison block 22, the first block 23 of the semi-permanent memory the display block 24, the third block 25 of semi-permanent memory, second register 26, t This pulse counter 27, fourth decoder 28, logical zero generator 29, switch 30, third switching unit 31, third decoder 32, shift register 33, second comparing unit 34, generator of 35 logical units, second switching unit 36 third register 37.

The device works as follows.

The first clock of the pulse generator 1 is counted by the first 2 and second 3 pulse counters, the counter 2 working on the leading edge of the clock and the counter 3 on the falling edge. On the leading edge of the first clock cycle, the switching unit 4 is opened and the initial (zero) value of the pulse counter 3 is entered into the register 5.

The following switching is performed: the analog-digital converter 10 code is connected to the first input of the RAM block 16, the output of the RAM block 17 is connected to the second input of the comparison unit 22, the output of the switching block 4 is connected to the address input of the RAM block 17 counter output 2 pulses connected

to the address input of the RAM 16, the first output of the decoder 20 is connected to the read input of the RAM 17;

The second output of the second decoder 20 is connected to the write input of the RAM block 16. In the first clock of the pulse generator 1, the decoder 6 issues a command to read the first set of full diagnostic test from the semi-permanent memory block 7, which is converted by the encoder 8 and is fed to the inputs of the diagnosed unit 9.

The output sequence of the signals of the diagnosed unit 9 is converted by the analog-digital converter 10 to a single digital form and is stored in the operational memory unit 16. A command generated by the counter 2 and the decoder 6 reads the zero records from the RAM block 17 and the semi-permanent memory block 23 and compares them by the comparison block 22.

The second clock of the generator 1 pulses is counted by the counters 2 and 3 pulses. At the leading edge of the second clock about, the switching unit 4 closes and the value of the pulse counter 3 is entered into the register 5 in the unit 5.

 The following switchings are made: the output of the analog-digital converter 10 is connected to the information input, the operating memory unit 17, the output of the operational memory unit 16 is connected to the first input of the comparison unit 23, the output of the switching unit 4 is connected to the address input of the operating memory unit 16; - the output of pulse counter 2 is connected to the address input of the RAM block 1 7, the first output of the decoder 20 is connected to the read input of the RAM memory block 16, the second output of the decoder 20 is connected to the input the recording of the second block 17 of RAM. In the second clock cycle of the pulse generator 1, the decoder 6 issues a command to read from the block 7 of the semi-permanent memory of the second set of the full structural diagnostic test, which is converted by the encoder 8 into a sequence of control

0

five

i

3 -

influences and is fed to the inputs of the diagnosed unit 9. The output sequence of the signals of the diagnosed unit 9 is converted by the analog-digital converter 10 to a single digital form and stored in the operating memory unit 17. At the command of the decoder 6, the records of the output sequences of the diagnosed unit 9 are read the inputs of the last first set of structural diagnostic tests, from the RAM block 16 and the semi-permanent memory block 23, and are performed Their comparison by unit 22 comparison.

If these sequences do not match, the command of the comparison unit 22 is triggered by the decoder 28, and the switching unit 31 is opened and the decoder 32 is started.

At the next start, the decoder 28 introduces commands for reading the sets of decryption dependencies to block 25 of the semi-permanent memory, and the address part of reading the sets of interpreting dependencies generates a counter 27, and the contents at this address are read into the register 26. The command of the counter 32 times -. the required switch of the read record in the shift register 33 is allocated by the serial switch 30, the remaining bits of this record are zeroed by the logical zero generator 29. In the shift register 33, the selected bit is shifted to the right under the control of the decoder 32. The comparison block 34 contains the contents of the selected bit compared with the logical unit generated by the generator 35 of the logical unit. When comparing the SRI, the register 37 through the block 36 of the mutation records the address of the set formed by the counter 27. If the block 34 compares the comparison, a command is issued to erase the record with this address from the block 25 of the half-state memory.

After the clock decoder 6 enters the input, the number of which is counted by counter 2 is (N + 1), where N is the number of test sets, the first decoder 6 performs the following operations: issues a command to the control input of the pulse generator 1 to turn it off; leads team42918 .4

do on the inclusion of the display unit 24, which shows the contents of the register 37 with the address of the failed element of the diagnosed unit 9.

five

Claims (1)

Invention Formula A control system diagnostic device comprising a generator 0 pulses connected to the output control inputs of the first, second, third, fourth, and fifth switches, to the counting input of the first pulse counter, to the control 5 to the input of the first switching unit and to the counting input of the second pulse counter connected to the discharge outputs by the information input of the first switching unit connected by the output to the input of the first register and to the information input of the third switch connected by the output to the first inputs of the first and second elements And connected by the second inputs F1 to the output the second switch, and the outputs to the address inputs of the first and second memory blocks, respectively, connected by information inputs from the output of the First switch, and the outputs from the info the sixth switch connected by the control input to the output of the first pulse generator, and the output to the first input of the first block compared to the second input connected to the output of the first block of the semi-permanent memory connected by the read control input to the first output of the first decoder, and address inputs MI to the inputs of the first decoder and to the discharge outputs of the first pulse counter, to the address inputs of the second block of the semi-permanent memory, to the information input of the second 0 five switch and to the inputs of the second a decoder connected by the first and second outputs to the information inputs of the fourth and fifth switches, respectively, connected by the outputs respectively to the read and write control inputs of the second and first blocks of RAM, the analog-to-digital converter connected by the input to the device input, and the output to the information input of the first switch, the encoder associated with the output to the device output, and the input to the output of the second unit of semi-permanent memory connected by a control input by a read to the second output of the first decoder connected by a third output to the control input of a pulse generator, as well as a third pulse counter, a second switching unit, a second comparison unit, a display unit, characterized by the fact that, in order to improve the speed of the device, a third block of semi-permanent memory, a second register, a low-level switch, a logical zero generator, a generator of a logical unit, a 5 shift register, a third register, a third the encoder, the third switching unit and the fourth decoder connected by the input to the output of the first comparison unit and to the control input of the third switching unit, and the output to the input of the third write terminal and to the counting input of the third pulse counter, the connected split bottom of the outputs with the information input of the second switching unit and with the address input unit of the semi-permanent memory, which is controlled by the control input 186 the first output of the second comparison unit, and the output to the information input of the second register connected by the control input with the output of the third decoder, with the control inputs of the bit switch and the shift register, and the outputs with the first information and bits of the bit switch connected by the second information inputs to the outputs of the logical zero generator, and outputs to the installation inputs of the shift register connected to the first input of the second comparison unit, connected, the second input The second output is connected to the control input of the second switching unit connected to the third register input connected to the information input of the display unit connected by the control input to the fourth output of the first decoder, the information input of the third block switching is connected to the output of the first register, and. you are a move to the entrance of the third decryption - rator. life, VNIIPI Order 3704/46 Circulation 836 Subscription Random polygons pr-tie, Uzhgorod, st. Project, 4 Subscription st. Project, 4