SU1287187A1 - Checking device - Google Patents

Abstract

This invention relates to computational instrumentation technology and can be used for monitoring. The purpose of the invention is to increase the speed of the device. This goal is achieved by introducing into the known device of the pulse generator, from the first to the seventh elements AND, the second and third decoders, the element and the group of OR elements, the first and second groups of elements AND with their connections by providing automatic collection and output of information. 1 il.

Description

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The invention relates to computational instrumentation technology and can be used to unify the equipment under development and shorten the time it takes to find faults.

The goal is to increase the speed of the device.

The drawing shows a diagram of the proposed device.

The device contains the second decoder 1, the first element And 2, the element And 3 of the second group, the second through the fourth elements And 4-6, the first decoder 7, the counter 8, the fifth element And 9, the generator 10 pulses, the element OR 11, the trigger 12, sixth and seventh elements AND 13, 14, first subscriber 15, first switch 16, group counter 17, group OR element 18, first group AND elements 19-22, third decoder 23, group memory blocks 24 and 25, AND elements 26.27, first group, elements OR, 28, 29 groups, counters 30 and 31 groups, elements AND 32, 33 of the second group, second switchboard and subscriber 34, 35, t The switch and subscriber's switchgear 36, 37, AND 38 element of the second group, nth switch 39, group counter 40, nth switch 41, OR group element 42, AND 43, 44 elements of the first group, triggers 45-48, AND elements 49-54, triggers 55-58, elements I-59-64, interface 65, address inputs 66, controls 67, Connection 68, Recording 69, Reset 70, data inputs-outputs 71, counter group 72, T ruppa of elements OR 73, the first and second groups of elements AND; 74, 75, a group of memory blocks 76.

The device works as follows.

Data is recorded specified information about controlled objects.

To reset the blocks 24 and 25 of the memory, signals are sent from the addresses 66 and from the reset 70 inputs. When the K-th output of the decoder 23 is energized, elements 13 and 14 are prepared for opening. Record on the bus 69 And 13 opens and his

output signal trigger 12 is set to one state. The signal taken in this case from trigger 12 prepares element 9 for opening. Pulses from generator 10 pulses go to counter 8, signals from which go to decoder 7. Output signals from decoder 7 the states of the memory elements in the memory blocks 24 and 25 are sequentially polled. The read information is recorded in the counters 17, 30, 31, 40, previously in which the setpoint is recorded depending on the number of control objects.

Counters 17, 30, 31, 40.vyschat signals at the output when they overflow, which are received at the corresponding switches 16, 34, 36, 41, in this case, connecting subscribers 15, 35, 37 to the interface.

To write the setpoint, a code is supplied to the decoder 35 23 that provides the excitation of the K + 1 output. When there is a signal at the input 69 Recording information from the data input 71 goes through the AND 4.5 elements into the counters 17, 30, 31, 40. The control overflow of the counters 17, 30, 31, 40 enters the input 66 of the address, which through the decoder 1 and the element And

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2, opened by a signal from input 68 The number of blocks of 24 memory is determined by 45 Readings, goes to the elements

And 3-, 32, 33, 38 through which information is read into the input-output 71 of the data.

depends on the number of controlled objects of control. The number of triggers in the row of memory blocks 24 is determined by the maximum number of checks or the object of control. The number of triggers in a column is determined by the number of systems involved in all possible checks performed. Before the start

50 When K + 1 output is excited in the decoder 7, the signal goes through the OR 11 element to the control input of the counter 8 and to the reset input of the trigger 12, which is fed to the initial operation in the blocks 24, 25 of the memory using the 55 state. The impulse passing through the decoder 23 is reportedly stopped by the generator 10 from the address 66 inputs, and up — the device operates in the display mode 67 (i.e., if there is a fault signal, it is the same as the input 69 Record), the inputs 71 watched.

Data is recorded specified information about controlled objects.

To reset the blocks 24 and 25 of the memory, signals are sent from the addresses 66 and from the reset 70 inputs. When the K-th output of the decoder 23 is energized, elements 13 and 14 are prepared for opening. Record on the bus 69 And 13 opens and his

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output signal trigger 12 is set to one state. The signal taken in this case from trigger 12 prepares element 9 for opening. Pulses from generator 10 pulses go to counter 8, signals from which go to decoder 7. Output signals from decoder 7 the states of the memory elements in the memory blocks 24 and 25 are sequentially polled. The read information is recorded in the counters 17, 30, 31, 40, previously in which the setpoint is recorded depending on the number of control objects.

Counters 17, 30, 31, 40.vyschat signals at the output when they overflow, which are received at the corresponding switches 16, 34, 36, 41, in this case, connecting subscribers 15, 35, 37 to the interface.

To write the setpoint, a code is supplied to the decoder 5 23 that provides the excitation of the K + 1 output. When there is a signal at the input 69 Recording information from the data input 71 goes through the AND 4.5 elements into the counters 17, 30, 31, 40. The control overflow of the counters 17, 30, 31, 40 enters the input 66 of the address, which through the decoder 1 and the element And

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The connection of subscribers 15.35,37 to the interface 65 is determined by the information recorded in the blocks 24 and 25 of the memory and the counters 17, 30, 31, of the AO pulses.

The use of the invention allows to increase the speed of the device by automating the process of collecting and reading information.

Claims (1)

Invention Formula A control device containing a counter, the outputs of which are connected to the corresponding inputs of the first decoder, a trigger, a group of memory blocks and a group of counters, is connected with the fact that, in order to increase the speed of the device, a pulse generator is introduced , from the first to the seventh And elements, the second and the third decoders, the W elements, the group of elements OR, the first and second groups of elements AND, the inputs of the second and third decoders are the corresponding address inputs of the device, the outputs of the second decoder are connected to the group of inputs of the first element I, the group of outputs of the third decoder to the address inputs of the memory blocks, the first output to the first inputs of the elements I from the second to the fourth, the second inputs of the second and third elements I are the corresponding data inputs of the device, the third inputs are the input Record of the device, the input of the first element I. Is the input Read the device, the second input of the fourth element I is the input 0 five 0 five 0 five 0 The device reset, the output of the pulse generator is connected to the first input of the fifth element And, the second input of which is connected to the trigger output, the second output of the third decoder is connected to the first inputs of the sixth and seventh elements And, the first input of the sixth element And inputs Writing memory blocks These groups are the Record input of the device, the second input of the seventh And element and the reset inputs of the memory blocks of the group are the Reset input of the device, the output of the fifth And element is connected to an account and the counter input, the output of the sixth And element is connected to the input set in 1 trigger, the output of the seventh element AND is connected to the first input of the OR element, the output of which is connected to the reset inputs of the counter and trigger, the output of the first decoder is connected to the second input of the OR element, the group of outputs of the first decoder is connected to the same inputs of the And elements of the first group, the other inputs of which are connected to the corresponding outputs of the memory blocks, and the outputs are connected to the inputs of the corresponding elements of the group WH, the outputs of which are connected to the counting inputs of the corresponding group counters, the outputs of watts And the third and elements are connected to the installation inputs of the group counters, and the output of the fourth element I is connected to the control inputs of the group, respectively, the outputs of the group counters are connected to one input of the elements AND group, the other inputs of which are connected to the output of the first element AND, and the outputs are device data outputs.