SU1173414A1 - Program control device - Google Patents

Abstract

SOFTWARE CONTROL, containing a pulse generator, a counter, first and second decoders, a memory unit, first and second groups of switches, trig. a ger, an And element, a delay element, an address register and an output register, the device mode control input connected to the control inputs of switches of the first and second groups and the memory write / read input of the memory block whose address inputs are connected to the outputs of the first decoder whose inputs are connected with the outputs of the address register, the first and second groups of information inputs of which are connected respectively to the outputs of the switches of the first and second groups, the input of the register of the address register is connected to the first output of the second decoder, the second and third outputs of which are connected respectively to the installation input to the trigger unit and the write input of the output register, the setup input of which is connected to the first input of the zero setting of the trigger, to the installation input of the counter and connected to the input of the initial installation of the device the second input of the zero setting of the trigger, the input of the delay element and is the output of the sign of the end of the device operation, the output of the delay element is connected to the reset input of the counter, counting input which is connected to the output of the element I, the first input of which is the input of the sign of the device’s start, the second input of the element I is connected to the output of the pulse generator, the information outputs of the counter are connected to the inputs of the second decoder the inputs of which are information inputs of the device (of the device, the outputs of the memory block are connected to the information inputs of the output register, the first group of outputs of which is the first group of device outputs, the first information inputs of the switches of the second group are connected to the second group of output register outputs, 00 4 the first information inputs of the switches of the first group are connected to the first group of device condition inputs, the second information inputs of the second group switches are connected to the second group that, in order to reduce the equipment by reducing the volume, it facilitates a group of multiplexers and a group of decoders, and the multiplex outputs eksorov group are connected with second information input sponding switches of the first group, the control inputs of multiplexers are connected to a group of the second group

Description

the outputs of the output register, the information inputs of the multiplexers of the group are connected to the third group of inputs of the device conditions, the third group

the outputs of the output register are connected via a group of decoders to the second group of information outputs of the device.

The invention relates to computing technology and can be used to build control and automatic machines for processing discrete information. The purpose of the invention is to reduce hardware by reducing the amount of memory. The drawing shows the functional scheme of the proposed device. The software control device contains a pulse generator 1, a counter 2, a second decoder 3, a first decoder 4, a memory block 5, the first group of switches 6-6 |, trigger 7, And 8, reset input 9, a group of information inputs 10-10 | y |, address register 11, output register 12, second switch group (, delay element 14, start sign 15, first condition condition group, second condition input group, mode control input 18, work end sign output 19, multiplexer group, group of decoders 21 21 (1, the first group of information these outputs are the second group of informational outputs 23.-23n and the third group of condition inputs. The device works as follows: Switches 6 and 13, depending on the value of the signal at input 18 of the device, switch one way or the other, and the memory block, depending on the value of The signal operates in the mode of recording information or reading it in. Before the device starts operation, it is necessary to record in the memory block 5 information about the operation algorithm of the device. For this, the signal O from the input 15 of the device prohibits the passage of pulses from the generator 1 through the element AND 8 to the counter 2, and the signal from the input 9 causes the trigger 7, the counter 2 and the register 12 to its initial state. Then the signals 1 are installed at the inputs 9 and 15 of the device. At the same time, the pulses from the generator 1 through the element 8 come to the input of the counter 2, from where in the parallel code to the decoder. 3, the number of counted pulses is fed, as a result, a pulse is fed to the input of register 11, which records the address specified on the inputs and 17j, -17 of the device. The address is decrypted by the decoder 4 and in block 5 of the memory a cell is selected, into which it is necessary to record information from the input buses 10 -10 | devices. Counter 2 continues to count and decoder 3 sets trigger 7 to a single value and write to memory block 5 is enabled. Then, the decoder 3 sets the trigger 7 to the initial state, which removes the callback signal from the memory block 5, and signals on output 19 that it is necessary to set new information for writing to the new address, through element 14 the counter 2 is reset to the initial state. Further, the process is repeated many times. After the information is recorded, signal 1 is fed to the device input 18, allowing information to be read, and switches 6 and 13 switch the outputs of the multiplexers 20 and the outputs of the register 12, respectively. Then the pulse signal O, the driving counter 2, the trigger 7 and the register 12 are fed to the initial state. The process of reading information from memory block 5 is similar to the process of writing and is controlled by generator 1, counter .2, decoder 3 and trigger 7. In this case, the readout addresses are determined by the combination of the signal

on the third group of outputs of register 12 and the corresponding inputs of 24 device inputs, which switch in this state to the input of switch 6. Multiplexers 20 switch to the input of switches 6 in each a. a state of no more than K input signals from a plurality of input signals N, and this is achieved by reducing the volume of the memory block by the input signals.

The output signals of the memory unit, which are fed to the inputs of the decoder 21, encode the output functions of the control unit. Moreover, the subgroups of output signals arriving at the inputs of the corresponding decoders are selected so that inside each of them the signals take on a value at times that do not coincide with its other members. This is a group of exits 23

devices. The output signals of the control device, for which coding cannot be carried out, are output | directly to the output device (group 22).

In a number of cases, it is not sufficient to have multiplexers with the number of switching inputs equal to the sexes, and less than the number of states of the memory of the automaton. In this case, part of the input variables switched by multiplexers is not analyzed in a state or analyzed twice in different states (for example, in state a, g - code 10011, state a code 00011), which must be taken into account when encoding the states of the automaton and the programming of the switching functions recorded in the memory block.

Claims (1)

SOFTWARE CONTROL DEVICE, containing a pulse generator, counter, first and second decoders, a memory unit, the first and second groups of switches, trig. ger, AND element, delay element, address register and output register, the device mode control input connected to the control inputs of the switches of the first and second groups and the write-read input of the memory block, the address inputs of which are connected to the outputs of the first decoder, the inputs of which are connected to the outputs of the address register, the first and second groups of information inputs of which are connected respectively to the outputs of the switches of the first and second groups, the input of the address register record is connected to the first output of the second decoder, the second 'and the third outputs of which are connected respectively to the installation input to the trigger unit and the input of the output of the output register, the installation input of which is connected to the first input of the installation to zero the trigger, with the installation input of the counter and connected to the input of the initial installation of the device, the fourth output of the second decoder is connected with the second input of the zero setting of the trigger, the input of the delay element and is the output of the sign of the end of the device, the output of the delay element is connected to the reset input of the counter, the counting input of which is Inonii yield AND gate, a first input of which is the input feature starts working device, the second input of AND gate connected to the output of the pulse generator, data outputs of the counter are connected to inputs of the second decoder, the output latch coupled to the input of the circulation permits _a memory information input ® are the information inputs of the device, the outputs of the memory block are connected to the information inputs of the output register, the first group of outputs of which is the first group of information outputs devices, the first information inputs of the switches of the second group are connected to the second group of outputs of the output register, the first information inputs of the switches of the first group are connected to the first group of inputs of the device conditions, the second information inputs of the switches of the second group are connected to the second group of inputs of the device conditions, characterized in that, with the purpose of reducing equipment by reducing memory, it contains a group of multiplexers and a group of decoders, and the outputs of the multiplexers of the group are connected to the second information inputs of the respective switches of the first group, the control inputs of the multiplexers of the group are connected to the second group SU „..1173414 outputs of the output register, the information inputs of the group multiplexers are connected to the third group of inputs of the device conditions, the third group of outputs of the output register is connected through the group of decoders to the second group of information outputs of the device.