SU1764055A1 - Device for information testing - Google Patents

Abstract

The invention relates to automation and computing and can be used to control the sequence of digital data when processed in an automated way. The purpose of the invention is to increase the speed of the device due to the fact that the reading of reference information occurs in zones belonging to certain recipients. The device contains a clock pulse generator 1, a decoder 2, comparison blocks 3, 12, a block of 4 memory of reference addresses, two groups 5, 7 on p registers, switches 6, 10, element OR 8, delay elements 9, 17, counter 11, three trigger 13, 16, 18, the element NOT 14, the element OR 15, the elements AND 19, 20, the display unit 21, the driver 22 pulses. The incoming information is divided into address and information parts. The analysis of the address part occurs in the decoder, and if the address is unresolved, the corresponding indicator is displayed in the display unit. When determining the address, the reference information is read from the corresponding zone of the memory block and compared in the comparison block. In case of incomparability of information in the display unit, the corresponding indicator is displayed. 2 Il. THX

Description

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The invention relates to automation and computing and can be used in diagnostic systems to control the sequence of digital data when processed in an automated way.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the functional diagram of the device; figure 2 is a functional diagram of the switch.

The device contains a clock pulse generator 1, a decoder 2 (addresses), a first comparison unit 3, a reference address memory block 4, a group 5 of n registers, a switch 6, a group 7 of n registers, the first element OR 8, the first delay element 9, switch 10, address (memory) counter 11, second comparison block 12, trigger 13, NOT element 14, second element OR 15, trigger 16, second delay element 17, trigger 18, two elements AND 19, 20, display unit 21, pulse shaper 22.

Registers from groups 5, 7, counter 11 contain log2N bits, where N is the volume of memory block 4.

Blocks 3, 12 comparisons can be built, for example, on 133SP1 or 533SP1 microcircuits.

Switches 6, 10, the functional scheme of which is shown in figure 2, contain a group of n elements OR 23i-23n, n groups of elements And 24i-24n.

The device works as follows.

Before starting work, a reset pulse arrives at the device's reset input, which zeroes the triggers 13,16,18, counter 11, and the trigger 16 is reset via the OR 15 element. The memory of the reference addresses is divided into zones with initial and final addresses, with this number of zones is equal to n (the number of allowed addresses coming in the address part of the word of digital data). The starting addresses of all zones are entered into the first group of registers 7i-7n, the ending addresses into the second group of registers 5i-5n. The digital word arriving at the device input contains the address part arriving at the inputs of the address decoder 2, and the information part entering the first group of inputs of the first comparison unit 3. Depending on the code of the selected address, one of the outputs of the decoder 2 is excited, and through the switch 10, the initial address of the corresponding zone of the reference memory 4 is written to the counter 11 from the corresponding register 7i-7n by a pulse from the output

shaper 22 pulses. In addition, a high level from the excited output of the decoder 2 addresses through the element OR 8 and the element NOT 14 closes the element AND 20,

prohibit indication. When a forbidden address code arrives at the input of the decoder 2, none of the addresses of the decoder 2 address is energized and a low level through the element NOT 14 opens the AND element

0 20, which at the first input will be opened by a high level from the zero output of the trigger 13. In the display unit the absence of the resolved address will be indicated. Let the resolved address come, then

5, the high level from the output of the element OR 8 through the pulse shaper 22 sets the trigger 16 to one state. The high level from the output of the trigger 16 through the delay element 9, the delay time of which is determined by the stable operation of the switch 10, the counter 11, the memory block 4 and the comparison block 3 enables the operation of the clock generator 1. In this case, until the generator 1 of these 5 pulses is started, the memory 4 is read at the address written to counter 11 from the registers. At the control input of the memory block 4, there is at the same time a high-level permitting potential from the inverse output of the 1-clock pulse generator. At the second inputs of the first comparison unit 3, the contents of the cell of the memory 4, read at the starting address, are fed. At the first inputs there is an informative part of the word of digital data from the group of inputs of the device. If the reference information from the memory block 4 and the input device has been compared, the block 3 is triggered.

0 comparison, and the signal that appeared at the output sets trigger 13 to one state. The signal from the output of this trigger prohibits the operation of the display unit and, through the OR element 15, resets the trigger

5 16, prohibits the operation of the generator 1 clock pulses. In the event that the comparison of information in block 3 comparison did not occur, the generator of 1 clock pulses is started, which translates the counter 11 into

0 next state. A reading of block 4 of memory takes place, and so on until the moment of operation of unit 3 of comparison, the signal from the output of which prohibits the operation of the display unit and stops the generator 1 of such 5 pulses. If the comparison of the reference and the received information did not occur until the moment when the counter 11 assumes a state equal to the final address of the zone, then the comparison unit 12 will operate. The signal from the output of block 12 comparison through

a delay element, the time of which is determined by the operation of memory block 4, comparison unit 3, sets trigger 18 to one state, opening AND 19 on the second input, the first input of which has a high level from the output of trigger 13. The display unit will display incomparability of the information part of the digital words, and with the standard. When the next word of digital data is received, the work proceeds as described.

Thus, if the reference information is recorded in the i-th cell of the memory block 4, the speed is increased by the time T (AND), where i takes a value from 1 to N; T is the reading time of one cell of the memory unit 4 of the prototype and processing of the information of the cell read; N is the number of cells in the memory block 4,

Claims (1)

Claims An information monitoring device comprising an indication unit, two AND elements, a NOT element, two comparison blocks, a reference address memory block, the group of information outputs of the device connected to the first group of inputs of the first comparison block, the output of the first And element connected to the first input Display unit, characterized in that, in order to improve speed, the device contains a decoder, a clock generator, two groups of registers, the first and second switches, the address counter, the first and second e OR, first, second and third triggers, first and second delay elements, pulse shaper, the group of address outputs of the device connected to the group of inputs of the decoder, the outputs of which are connected to the control inputs of the first, second switches and inputs of the first OR element whose output is connected with entrances the element NOT and the pulse former, the output of which is connected to the resolution input of the address counter and the single input of the first trigger whose output is connected through the first delay element with the start input of the clock generator, the direct output of which is connected to the counting input of the address counter, and the inverse output to the read input of the memory block reference addresses, the output group of which is connected to the second group of inputs of the first comparison unit, the output of which is connected to the single input of the second trigger and the first input of the second element OR, the second input of which is connected to the zero inputs of the second and third triggers, the reset input of the address counter and the device reset input, the third input of the second element OR is connected to the output the second comparison unit and through the second delay element - with the single input of the third trigger, the output of which is connected to the first input of the first element And, the second inputs of the first and second elements And connected to the inverse output of the second trigger, the first input of the second element AND connected to the output of the element NOT, the output of the second element OR connected to the zero input of the first trigger, the outputs of the registers the first and second groups are connected to the information inputs of the first and second switches, respectively, the group of outputs of the first switch is connected to the group of information inputs of the counter the address, the information output group of which is connected to the first input group of the second comparison unit and the address input group of the reference address memory block, the first input group of the second comparison unit is connected to the output group of the second switch, the output of the second And element is connected to the second input of the display unit. To fleas Ш2 G. LT g -, .. I I III I. I ii M / 1 | ( Si / g /%; 23, L BUT I By Rep. D / e.2