SU590825A1 - Coder - Google Patents

Description

one

The invention relates to computing and can be used in automated systems for managing, controlling and processing information.

An encoder is known that contains memory cells whose outputs are connected to the inputs of read elements.

When reading the code from the read elements, the output of the encoder contains information on all input signals, regardless of whether the input signals are received or not. The weakness of the encoder consists in the excess information, which reduces the speed of the system as a whole.

The encoder of addresses of input signals closest to the invention is also known, which contains memory cells whose outputs are connected to the first input of the corresponding read elements, the second inputs connected to the read resolution bus, reset signals, which outputs are connected to the inputs of the corresponding memory cells, and the decoder 2

The disadvantage of a known encoder is the long time it takes to read all the addresses, since all the addresses of the memory cells are read, regardless of whether the input signal arrives on it or not.

The purpose of the invention is to increase the speed with which we shorten the total time for reading addresses. This is achieved by introducing input signal drivers into the encoder, the inputs of which are connected to the outputs of the respective read elements, and outputs to the inputs of the decoder and the inputs of the corresponding reset signal drivers, and

OR elements, the first inputs of which are connected to the outputs of the corresponding memory cells, except for the first one, the second input of the first element OR is connected with the output of the first memory circuit and with the third input of the subsequent one

the read element, and the outputs of all the OR elements with the second inputs of the subsequent OR elements and with the third inputs of the subsequent reading elements. Such a device is allowed to get on

the output of the decoder is the address codes of only those memory cells that received input signals.

The drawing shows the scheme of the encoder.

The encoder contains 1, 2, 3 memory cells connected by outputs to the first inputs of read elements 4, 5 and 6, the second inputs of which are connected to a read resolution 7. Readout outputs

connected to the inputs of the formers 8, 9, and 10 of the input signals, the outputs of the drivers of the input signals to the inputs of the decimator 11 and the inputs of the formers 12, 13 and 14 of the reset signals, and the outputs of the formers of the reset signals to the second inputs of the memory cells 1, 2 and 3. Cells 2 and 3 of memory are connected by outputs to the first inputs of the corresponding elements OR 15 and 16. The output of the element OR 15 is connected to the second input of the subsequent element OR 16 and the third input of the corresponding reading element.

One input of the element OR 15 is connected to the output of the memory cell 1, the other input to the output of the memory cell 2. The input of the device is memory cells 1, 2, and 3, to which the input signals are received, and the output is decipheror 11; from its output, the code signals of the addresses of the memory cells, which received the input signals, are removed.

The encoder works as follows.

The input signals are stored on the cells 1, 2 and 3 palM TP, the output signals of which open the elements 4, 5 and 6 of the reader. The signals from the read bus 7 pass through the read element 4 and are fed to the shaper 8 of the input signals. The output signal from the imaging unit 8 is provided to the decoder 11 and to the imaging unit 12 of the reset signals. On decoder 11, the signal is converted into the code of the address of memory cell 1 and from the output of the decoder to the output of the device. The signal from the output of the reset signal generator 12 enters the input of the memory cell 1 and sets it to the "O" state. The signal from the readout bus 7 through the readout elements 5 and 6 does not pass, as they are closed by a prohibitory signal arriving at their third input. After being installed in the memory cell 1, the readout element 5 is opened, and the signal from the read bus passes through the formers 9, 13 and the decoder 11 in the same way as the signal from the readout element 4. By reading the address of the memory location 2, a similar process occurs to the reading of the location of memory location 3.

If the input signal is not received on the memory cell, the corresponding read element is not opened, and the address code of the corresponding memory cell on the decoder output is absent.

The technical and economic effect is that this encoder provides addresses only to those memory cells that received input signals, and the efficiency of the encoder’s operation is determined by the number of readable addresses per allowed time tick in the system. For control systems with

the short response time, the number of readable addresses is a few percent of the total. Thus, the efficiency of the encoder, defined as a reduction in the time to read an address, is increased tenfold.

Claims (2)

1. Module for inputting the signals of MVIS A622-4 complex of technical means M-6000 ASVT-M.TU.25.01.698.72. 2. USSR author's certificate number 347739, cl. G 05B 23/02.