SU955009A2 - Data input device - Google Patents

Description

(DEVICE FOR ENTERING INFORMATION

Claims (2)

The invention relates to computing and can be used to enter information in a system for processing measurement information. According to the main auth. No. a device for entering information is known that selects messages from the transmitted word. This device contains a data register and serially connected address register, a memory block connected to the interface block, a scaling node, first and second number registers, inputs connected to the memory block, and outputs to the first and second decoders, the first and second blocks. transfer the numbers connected respectively to the first and second decoders, the block of elements AND, connected by its inputs to the data register and both blocks of transfer of the number a and output to the scaling node, control block 1. The disadvantage of the known This is because it takes extra programming time to calculate the direction and magnitude of the shift. The purpose of the invention is to increase the speed of the device. The goal is achieved by introducing the first and second subtractors, a multiplexer, element 2 AND-2 OR-NOT and the third register whose input is connected to the memory unit, the output of the third register connected to the first inputs of the first and second subtractors, the second inputs of which connected to the output of the second register, the first outputs of the first and second subtractors are connected to the first and second inputs of the multiplexer, the output of which is connected to the second input of the scaling unit, the third and fourth inputs of which are connected to the third and fourth multiplexer rtym inputs, the first and second outputs of item 2 and 2 NOR inputs are connected to the second and third of outputs of the first and second you; readers, fifth and sixth inputs of block scaling connected to the first and second by control buses. In addition, the scaling unit contains an annular reversing deposit register, a subtracting counter, a trigger and an element, the first input of which is the fifth input of the stacking unit, the first input of the subtractive counter is the first input of the scaling unit, the second input of the subtracting counter is the poles by the input of the scaling unit and connected to the first input of the trigger, the output of which is connected to the second input of the element I, the output of which is connected to the first input of the ring reversing shift register and to the third input ychitayuschego counter output is connected to the second input of the trigger, second, third and fourth inputs and an output ring reversible shift register are the second, third and fourth input and output of the scaling unit. Figure 1 shows the structural diagram of the proposed device; in fig. the format of control words in FIG. 3 is a block diagram of a scaling unit. The device for entering information contains the data register 1, the address register 2, the memory block 3, the first, second and third registers k-6 of the number code, the first and second decoders 7 and 8, the first and second blocks 9 and 10 of the number transfer, the block elements in the AND, the first and second subtractors 12 and 13. the motor type 1, the element 2 and -2 OR-NOT 1 scaling unit 16, the first control bus 17 and 1 common bus 19 of the memory block. The device control word contains the following fields: 20 — code of the right border of the selected parameter; 21 code of the left border of the selected parameter; 22 - the position of the senior bit. yes select the embo parameter; service information The scaling unit 16 contains a ring reversing shift register -26, a subtractive counter 27. trigger 28 and element 29 I. The device operates as follows. The control system, using the common buses 19 of the memory block 3, loads this block with the control program. Then, reception of input messages from the measurement system begins. Each input message contains data loaded into register 1, and the address that is loaded into register 2. The address identifies the data type of the input message. At the address recorded in register 2, the control word is read from the memory block. In this case, control fields 20 and 21 and 22 are loaded into the first, second and third registers A-6, respectively. The contents of fields 23-25 of the control word define the processing mode of the original message and are analyzed by the control system. The contents of registers 5 and 6 are fed to the inputs of subtractors 12 and 13. Subtractor 12 subtracts the contents of register 5 from the contents of register 6, and subtractor 13 subtracts the contents of register 6 from the contents of register 5. Each of subtractors 12 and 13 has three outputs, the first of which is the output of the result, the second is the exit of the loan, and the third is of the highest order. The output codes of both subtractors arrive at the first inputs of multiplexer 1, where the output signals of element 15 select the result of one of the subtractors 12 and 13. At the same time, the outputs of element 15 control the direction of shift in block 16. After the start signal is received, bus 18 goes to the counter 27 of block 16, the code from the outputs of multiplexer k is recorded and simultaneously the trigger 28 is set to such a state that permits the passage of the clock pulses of the bus 17 through the element 29 And to the first (subtractive) input of the counter 27 and to the third Shift input of register 26. Signals from outputs of element 15 control the direction of shift of register 26. Shifts continue until counter signal appears in counter 27, which sets trigger 28 in opposite state, blocking the passage of clock pulses through element 29 I. The proposed device simplifies programming, freeing the programmer from calculating the direction and magnitude of the shift. As the time required to execute a single command by a device largely depends on the amount of shift, reducing the number of shifts to half the input word word increases the device’s speed by about 15 to kQ% depending on the number of parameters to be selected for which the number of shifts is more than half input word. Claims 1. Device for inputting information on the author No. Ytfi S, characterized in that, in order to increase the speed of the device, the first and second subtractor multiplexer, element 2 AND-2 OR-NOT and the third register, whose input is connected to the memory block, the output of the third register connected to the first inputs of the first and second subtractors, the second inputs of which are connected to the output of the second register, the first outputs of the first and second subtractors are connected to the first and second inputs of the multiplexer, the output of which is connected to the second input of the scaling unit, the third and fourth inputs of which connected to the third and fourth inputs of the multiplexer, to the first and second outputs of element 2 AND 2 OR NOT, the inputs of which are connected to the second and third outputs of the first and second subtractors, the fifth and sixth inputs of the scaling unit are connected to the first and second control buses. 2. The device according to claim 1, which means that the scaling block contains an annular reversing shift register, subtracting counter, trigger, and an element whose first input is the fifth input of the scaling block; The first input of the scaling unit, the second input of the subtracting counter is the sixth input of the scaling unit and connected to the first trigger input, the output of which is connected to the second input of the And element, the output of which is connected to the first input of the ring reversing sd the flashing register and with the T0 input of the detracting counter, the output of which is connected to the second trigger input, the second, third and fourth inputs and the output of the ring reverse shift register are the second, third and fourth inputs and output of the scaling unit. Sources of information taken into account during the examination 1. USSR Author's Certificate No., cl. G 06 F 3/00, 1978. (prototype). / 7 YU (Rig.y. V u j / 2 g / h / 7 fie.Z