SU824193A1 - Extremum number determining device - Google Patents

Description

The invention relates to automation and computing and can be used in information measurement systems for determining the extreme values of parameters in the process of their measurement.

A device for comparing binary numbers is known, which contains bitwise comparison blocks, OR-NOT elements OR elements, and a switch l.

The disadvantage of this device is the complexity and low speed.

Closest to the proposed technical solution is a device for determining extreme numbers, comprising a counter, two comparison blocks, a match element, two triggers, and two OR elements.

In this device, the determination of the extremal of the two input numbers is carried out at the moment of comparing the value of one of them with the contents of the counter / that works on adding from the zero value when determining the minimum number or on subtracting from the maximum possible number when determining the maximum number. The device spends the number of cycles for one cycle of operation.

determined by the codes of the incoming numbers 2.

The disadvantage of this device is its low speed.

The purpose of the invention is to increase the speed of the device.

This goal is achieved by THAT. In a device for determining extreme numbers containing pe0. the gist, the adder, the elements AND, OR, NOT, the switch, the information inputs of the device connected to the first groups of information inputs of the adder and the register, the inverse 5 register outputs connected to the second group of inputs of the adder, the low-order transfer of which You-, the transfer of the adder is connected to

Claims (2)

0 by the first input of the switch, and through the element NOT to the second input of the switch, the third input of which is connected to the first input of the AND element, the second input of which is connected to the control input of the device, and the output of the AND element connected to the first input of the OR element, the second input ; which is connected to the input of the initial installation of the device, the output of the OR element is connected, 0 to the register synchronization input. The drawing shows the functional diagram of the device. The device contains element 1 AND, element 2 OR, register 3, adder 4, element 5 NOT, switch 6, input information inputs 7, input 8 of the initial installation, control input 9 and information outputs 10. The device operates as follows. In the upper (according to the drawing) position of the switch, the device operates in the selection mode of the maximum value, and in the lower position - the minimum value from the array of numbers supplied by the information inputs 7. Accordingly, before starting operation during the initial installation, in the first case, in the register) 3 the zero value of the code is recorded, and in the second case the maximum possible. For this purpose, the information input 7 sets the corresponding code value to the information inputs of register 3, and input 8 of the initial installation sends a signal of the initial installation, which, through element 2 OR, records the set code on the synchronization input to register 3. On the first inputs adder 4 through information inputs 7 information comes in the direct code, and to the second inputs in the additional one, since the inverse outputs of register 3 are connected to these inputs of the adder, and the transfer input of the lower bit of the sums the torus is connected to the logical level 1. In this case, the logical unit level appears at the transfer output of the adder in those cases when the code value of the number arriving at information inputs 7 is greater or equal to the code value that is currently stored in register 3 Thus, in the selection mode of the maximum value, the switch in the upper position when entering through the information inputs 7 a number code whose value is equal to or exceeds the level recorded in the register, the level of the logical unit of transfer of the adder is fed to the input element 1, permitting the passage of a write pulse from control input 9 to the synchronization input of the register 3. In this case, a register is written to the incoming code value. If the value of the received code is less than that recorded in the register, the recording is not performed because the input of the element 1 and from the transfer output of the adder prohibits the level of logic zero. When the device operates in the mode of selecting the minimum value (switch in the lower position), the signal from the transfer output of the adder enters element 1 and through element 5 NOT, which provides inverse conditions for recording information, i.e. the register then writes the value of the code, which is smaller than that currently stored in the register. In relation to the moment of arrival of information on information inputs 7, a write pulse on control input 9 is applied with a delay determined by the time for establishing the transfer signal at the output of the adder. Information about extreme values is output from the direct outputs of register 3 via information outputs 10. Thus, the proposed device is significantly faster, since the analysis of the incoming number is carried out per device operation cycle, the duration of which is determined by the transient time in the adder and the register, while in a known device it takes a number of clock cycles, determined by the values of the incoming numbers. Claims. A device for determining extreme numbers, containing a register, adder, AND, OR, NOT elements, a switch, the device's information inputs are connected to the first groups of information inputs of the adder and register, inverse outputs of the register are connected to the second group of inputs of the adder, whose lower-case carry input is connected with the bus of the logical unit, which is tl and tea, because, in order to increase speed, in it the transfer output of the adder is connected to the first input of the switch, and through the element NOT to the second the input of the switch, the third input of which is connected to the first input of the element AND, the second input of which is connected to the control input of the device, and the output of the element AND is connected to the first input of the element OR, the second input of which is OR connected to the input register synchronization. Sources of information taken into account during the examination 1. USSR author's certificate tf 489104, cl. G About F 7/04, 02.07.73. 2. USSR author's certificate number 643367, cl. G 06 F 7/04, 09.01.78 (prototype). 7R & SM Гп. eight 5oG YU