SU1083198A1 - Operational module - Google Patents

Abstract

OPERATING MODULE containing the first and second triggers, the synchronization inputs of which are connected to the synchronization input of the module, characterized in that, in order to expand the scope of application by implementing the module's adaptability to the problem being solved, the first and second groups of elements 2I-OR are introduced into it - NOT four elements in each, the element is NOT, the first and second memory blocks, groups of information inputs, the first groups of address inputs and the write resolution of which are connected respectively to the group of information inputs , -C upravleyi inputs and a control input of unit, second group of address inputs of the first and second memory blocks are connected to the outputs sootBeTCTBieHHo elements. 2 OR-NOT of the first and second groups, the first information outputs of the first and second memory blocks are connected respectively to the first input of the first element 2И-OR-NOT of the second group and to the module transfer output, the second information output of the first memory block is connected to the information input of the first trigger and-with-the first asynchronous data output of the module, the second information output of the second memory block is connected to the information input of the second trigger and the second asynchronous data output of the module, the first input of the first element 2I-OR-NO The first group is connected to the transfer input of the module, the first inputs of the second elements 2K-OR-NOT of the first and second groups are connected respectively to the first and second inputs of the module, the first input of the third element 2I-1ShI-KE i O) of the first group is connected to the output of the first trigger , with the transfer output to the right of the module and with the first synchronous data input of the module, the first input of the third element 2I-OR-NOT of the second group is connected to the first input of the fourth element 2I-OR-ME of the first group, with the output of the second trigger and the synchronous data output of the module, ne The fourth input of the fourth element 2I-OR-NOT of the second 00 gruppy is connected to the transfer input to the right of the module, the second inputs of the first, from the second, third and fourth elements 2I-Sh1I-NOT of the first and second groups are connected to the first, second, second, third and fourth, respectively. The inputs are module settings, the third inputs of all 2I-OR-NOT elements are connected to the output of the NOT element, whose input is connected to the fourth inputs of all 2I-OR-NOT elements and to the module mode control input.

Description

The invention relates to Highlighter technology and can be used in the construction of specialized and universal computers. A microprocessor module containing a register-battery, four groups of control commands, input and output data and function buses to the right and left, as well as the Cl1 clock bus is known. The disadvantage of this module is the wide field of control of the microoperation. Closest to the proposed technical entity is a microprocessor module that contains the first and second triggers, the sync inputs of which are connected to the clock bus, four multiplexers, the first group of control buses are connected to the information inputs of the first multiplexer, the first control input of which is connected with the first control input of the second multiplexer, the second control input of which is connected to the input transfer bus and the second control input of the first multiplexer, the third control The liaison input of which is connected to the first input data bus and the third control input of the second multiplexer, the fourth control input of which is connected to the output feedback bus, the first output data bus, the zero-output trigger output and the fourth control input of the first multiplexer, output which is connected to the first output transfer bus, the second output transfer bus is connected to the output of the third multiplexer, the first control input of which is connected to the input feedback bus and the first control named by the input of the fourth multiplexer, the second control input of which is connected to the first output transfer bus and the second control input of the third multiplexer, the third control input of which is connected to the second input data bus and the third control input of the fourth multiplexer, the fourth control input of which connected to the output of the first trigger / second output data bus and the first control input of the first multiplexer, the information inputs of which are connected to the first group of control buses, information The ion outputs of the second and fourth multiplexers are connected respectively to the D inputs of the first and second triggers, the first and second asynchronous data buses are connected respectively to the D inputs of the first and second triggers 2. A disadvantage of the known module is the inability to adapt to the problem being solved. The purpose of the invention is to expand the area of application of the module due to its realization of the possibility of adapting to the problem being solved and performing various operations in different categories. The goal is achieved. We note that the first and second triggers, the synchronization inputs of which are connected to the synchronization input of the module, are entered into the first and second ZI-OR-NO element groups with four elements each, the NOT element, the first and second blocks. memory, groups of information inputs, the first groups of address inputs and recording resolution inputs of which are connected respectively to the group of information inputs, to the group of control inputs and to the control input of the module, the second groups of address inputs of the first and the second memory blocks are connected respectively to the outputs of elements 2I-OR-NOT of the first and second groups, the first information outputs of the first and second memory blocks are connected respectively to the first input of the first element 2I-OR-NOT of the second group and to the transfer output of the module, the second the information output of the first memory block is connected to the information input of the first trigger and the first asynchronous data output of the module, the second information output of the second memory block is connected to the information input of the second trigger and the second async data output module, the first input of the first element 2I-OR-NOT the first group is connected to the transfer input module, the first inputs. second elements 2I-OR-NOT the first and second groups are connected respectively to the first and second data inputs of the module, the first input of the third element 2 OR-NOT of the first group is connected to the output of the first trigger, with the transfer output to the right of the module and with the first synchronous data input of the module, the first input of the third element 2 OR-NOT of the second group is connected to the first input of the fourth element 2 OR-NOT of the first group, with output the second, trigger and second synchronous data output of the module, the first input of the fourth element 2И-OR-NOT of the second group is connected to the transfer input to the right of the module, the second inputs of the first, second, third and fourth elements 2И-OR-NOT of the first and second groups connected to the first, second, third and fourth inputs of the module settings, the third inputs of all 2I-OR-NOT elements are connected to the output of the NOT element, whose input is connected to the fourth inputs of all 2I-OR-NOT elements and to the control input of the module mode.

The drawing shows a diagram of the proposed module.

Operational module contains the first. 1 and second 2 triggers, a group of control inputs 3, the first 4 and second 5 data inputs, the first 6 and second 7 asynchronous data outputs, the first 8 and second 9 synchronous data outputs, input 10 and output 11 pere-. of the nose, input 12 and output 13 of transfer to the right, input 14 of synchronization, four inputs 15-18 of the setting, input 19 of the mode control, element NOT 20, eight elements 2I-OR-NOT 21-28, two blocks 29 and 30 of memory, input 31 record permissions and a group of information inputs 32.

An operational module designed to implement arithmetic logic operations, works as follows.

The binary code supplied by the group of inputs 3 of the control determines the type of micro-operation implemented over two operands, one of which is located in triggers 1 and 2, and the other on inputs 4 and 5 of data. The number of control inputs is determined by the binary logarithm of the number of micro-operations selected from the entire set of possible micro-operations to solve this problem. To prepare the microprocessor module for the implementation of the selected set of micro operations, the configuration mode is used, determined by the value of the signal at the mode control input 19. In this mode, the second group of address input blocks 29 and 30 of the memory is connected. through elements 2I-OR-NOT 21,23,25, 27 and 22,24,26,28 with outputs 15,16 and 17,18 settings, respectively.

To configure the operating module for. the implementation of a certain micro-operation on the group of control inputs 3 sets the code of this micro-operation, and on settings 15-18, one of the possible sets of operand values, transfer and shift is right connected with the micro-operation. At the same time, the input signal 15 in the configuration mode is the transfer value, input 16 is the bit value of the input operand, input 17 is the trigger value 1 and 2, and input 18 is the transfer value to the right. At the same time, on one and the other pairs of bits of the group of information inputs 32, the values of the results of operations in the corresponding bits of the device and transfer to the next bits are set. After all these data have been installed, a signal is received at the input 31 of the recording resolution, which records the information received in memory blocks 29 and 30. In a similar way, the operating module is configured for all possible sets of operand and carry values for the entire selected set of micro-operations.

. After tuning, the operating module changes the signal at the mode control input 19 to the calculation mode. In this mode, the second group of address inputs of memory blocks 29 and 30 is connected by the corresponding outputs of flip-flops 1 and 2, inputs 4 and 5 of data, and inputs 12 and 10 of transfers. At the same time, the second outputs of memory blocks 29 and 30 and the asynchronous outputs 6 and 7 of data correspond to the one specified on the group of inputs 3

5 of the micro-operation control, the result of performing the micro-operation in the corresponding bit is formed, and at the first outputs - the value of the transfer signals. The value of the transfer signal

0 from the first output of the memory block 30 enters output transfer 11. Thus, the value of the result in this bit and transfer to the next bit for a given micro-operation are arbitrary switching functions of four arguments: a signal at the input 4 or 5 of the data of the corresponding bit, an output signal of the corresponding bit, a transfer signal coming at input 10 of the transfer or from the first output of the memory block 29 and the transfer signal to the right, coming from the output of the second nli at input 12 of the transfer to the right.

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On the front of the clock pulse, received by the input 14 synchronization input to the synchronization input of the triggers 1 and 2, the result of the micro-operation from the asynchronous outputs 6 and 7 of the data is recorded into the triggers 1 and 2. This

0 the result goes to the synchronous outputs 8 and 9 data. Simultaneously, the signal from the output of the first trigger 1 is fed to the output 13 of the transfer to the right. The result recorded in the trigger 1 and 2 remains unchanged until the arrival of the front of the next clock pulse.

In order to implement another subset of micro-operations, a tuning process must be repeated.

Thus, the proposed module realizes the ability to adapt to the problem being solved by carrying out the appropriate setting of a certain system of micro-commands, and also provides the ability to perform various operations in different bits.

The implementation of such opportunities allows to expand the scope of the proposed module. So, for example, on its basis one can construct a multi-bit adaptive processor with a set of realizable microoperations changing in the course of computations.

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Claims (1)

OPERATING MODULE, containing the first and second triggers, the synchronization inputs of which are connected to the synchronization input of the module, characterized in that, in order to expand the scope due to the implementation by the module of the ability to adapt to the task at hand, the first and second groups of 2-OR elements are introduced into it -NOT four elements in each, the element is NOT, the first and second memory blocks, groups of information inputs, the first groups of address inputs and recording permission inputs of which are connected respectively to the group of information inputs, shine control inputs and the control input of the module, the second group of address inputs of the first and second memories respectively connected to the outputs of elements. 2 OR-NOT of the first and second groups, the first information outputs of the first and second memory units are connected respectively to the first input of the first element 2 AND-OR-NOT of the second group and to the module transfer output, the second information output of the first memory unit is connected to the information input of the first trigger and · with the first asynchronous output of the module data, the second information output of the second memory block is connected to the information input of the second trigger and with the second asynchronous output of the module data, the first input of the first element 2 AND-OR-NOT the first groups are connected to the transfer input of the module, the first inputs of the second elements 2 AND-OR NOT the first and second groups are connected respectively to the first and second inputs of the module data, the first input of the third element 2 AND-OR NOT the first group is connected to the output of the first trigger, with the transfer output to the right of the module and with the first synchronous input of the module data, the first input of the third element 2 AND-OR NOT of the second group is connected to the first input of the fourth element 2 AND-OR-NOT of the first group, with the output of the second trigger and with the second synchronous output of the module data, the first input of the second element 2 AND-OR-NOT of the second group is connected to the right input of the module, the second inputs of the first, second, third and fourth elements of 2I-OR-NOT of the first and second groups are connected respectively to the first, second, third and fourth inputs of the module settings, third the inputs of all 2AND-NOT-NOT elements are connected to the output of the NOT element, the input of which is connected to the fourth inputs of all 2AND-OR-NOT elements and to the module mode control input. SU „L 083198