SU951315A1 - Device for interfacing processor with multi-unit memory - Google Patents

Description

The invention relates to computing and can be used to increase the amount of operational PS1 when building digital data processing systems based on a mini {micro -) computer.

A memory management device with paging organization is known that contains page address registers, page attribute registers, adders and switch 1.

The drawbacks of the device are a large amount of equipment and low speed due to the loss of time in each cycle of accessing the memory for the conversion of a virtual address into a physical one.

The closest to the proposed technical entity is a device for communication of storage and arithmetic devices with a memory address format that exceeds the address format of an arithmetic device containing a switch, serially connected decoder, encoder, registers, outputs KOTOjxjx are connected to a group of address inputs of a memory device and to the control inputs of the switch 2.

However, the known device does not provide the ability to work simultaneously with different memory areas located in its different pages without switching the register of the array number, which reduces the speed and limits the functionality of the device.

The purpose of the invention is to increase

10 speed device.

The goal is achieved by the fact that a decoder unit, a group of channel transceivers, are entered into the device for interfacing the processor with a multi-block memory containing the register of the array number and the memory block whose inputs / outputs are information inputs / outputs of the device

20 address decoder, trigger, control decoder, the first and second inputs of which are connected to the device control I / O group, and the third input 25 to the trigger output, the synchronous input of which is connected to the device control I / O group, and information input - to the output of the address decoder, a group of inputs

30 which is connected to a group of

the channel group of the channel transceivers and the group of inputs of the register of the array number, the output group of which is connected to the group of inputs of the dir unit and the first group of inputs of the group of channel transceivers, the second group of inputs of which is connected to the group of control inputs / outputs of the decoder unit connected to the group of control inputs of the memory unit; the second output of the decoder of the control signals is connected to the input of the group of channel transceivers.

Figure 1 shows the block diagram of the device; 2 is a block diagram of a control unit.

The device contains inputs / outputs of 1 memory block, control block 2, register 3 of the array number, decoder block; 4, memory blocks 5, memory banks 6, output groups of the 7 register of the array number 3, channel transceivers 8, address decoder 9, trigger 10, control signal decoder 11.

The device works as follows.

Each of the n memory blocks 5, containing m banks of 6 memory, has a maximum capacity corresponding to the format of the address word of the processor. Each of the banks of the six memory has a control input through which this bank is either allowed or prohibited to work with the bus. Due to the fact that each memory bank 6 is controlled autonomously, it is possible to connect a specific set of m banks of 6 memory blocks 5 to the backbone bus during a single processor cycle using the control unit 2 and the register 3 of the array number, Depending on the code array number transferred to register 3, a combination of banks, b of 5 memory blocks 5 is connected to the backbone. In this case, only such combinations of banks of 6 memory are possible, in which only one of the same-name banks belonging to different blocks of memory is connected. After passing the signal to the zero setting, the register 3 of the array number is set to the zero state. When the first output buses of each of the decoders 4 are received, control signals are received that only allow the banks of the first memory block to work with the backbone. The change of the memory bank combination connected to the trunk is made by changing the code at the outputs of register 3 of the array number. Writing the code in register 3 of the array number is done

programmatically, using a separate co. shipping mandates. In this case, with the help of decoders 4, a combination of banks 6 of the available n memory blocks 5 is connected to the trunk. Control of the connected combination

memory banks are implemented when reading the code from the outputs of register 3 of the array number via control unit 2 to the processor. Maximum capacity

Each memory block can have no more than 2 words, where N is the format of the address word of the processor. The control unit 2 is designed to interface the register 3 of the array number with the bus main bus. Performance

control block 2 is determined by the type and structure of the trunk. Therefore, its specific implementation for different computers may be different.

The control unit 2 includes channel transceivers (TLS), an address decoder (AAS), a trigger. The device is selected (TUB) and a decoder for control signals (DSURS).

Address codes and data for decoding the address in the BOTTOM and writing to the register 3 is received via the data bus address (SHADM) buses to the checkpoint inputs. From PPC outputs, address codes and data

tires data addresses (STD) are fed to the inputs of the beam. and register 3 numbers of the array. The transfer from register 3 of the number of the array of the code set in it to the SHADM is made via the checkpoint for the data buses (SM). The address synchronization pulse (CIA) with the coincidence of the address code received at the input gave, with the address code of the device for managing the memory trigger. The device selected is set to

t I I I state and allows the DSBU to work. To the input of the decoder 11 of the control signals are received the clock pulses of the data of the LED1 (data input) and LED2 (output

data). When the signal SID1 arrives at the DSUS input, the decoder generates a SIM signal, which is used to transmit the control code of the register 3 of the array number to the trunk. Upon receipt of the signal SID2 at the DSURS input, the decoder generates a write write synchronization pulse, using which a register is written in register 3 of the array number

next incoming code.

Thus, using the device in question, various combinations of m banks can be connected to the bus line of the common processor bus.

Ps1m ti. This reduces the frequency of access to the register memory management (register 3 of the array number of the proposed device) and provides more flexible use of memory

volume in excess of words for

Due to this, the speed of the device is improved compared with the prototype.

Claims (2)

1. Kagan BM, Electronic computers and systems. Energie, 1979, p. 461. 2. Authors certificate of the USSR 643878, cl. G About F 13 / 0b, 1979 (prototype). 41p 41: f duiomad g / f odujsmid ({/ I n {/ 0tlu / 3ni0lii) j