SU881725A1 - Device for interfacing computer with peripheral units - Google Patents

Description

I

The invention relates to computing, in particular, to devices for controlling the selection of the exchange mode and can be used in the construction of exchange systems.

A device for information exchange is known, which contains a buffer block, connected to the number register and address decoder, current address registers whose inputs are connected to the output of the buffer accumulator, and outputs to the input of the decoder and initial address register l.

However, this device has a slight speed due to the presence of the regeneration mode of the read information.

Closest to the invention in its technical essence is a device for controlling the selection of the exchange mode, comprising the first and second decoders, the first, second and third

registers, the first and second groups of elements And 23.

The disadvantage of this device is the impossibility of changing the exchange mode for the same peripheral object without re-entering the address of this object, which reduces the speed of information exchange with external objects.

The purpose of the invention is to increase the speed of information exchange.

This goal is achieved by the fact that the device for interfacing a computer with external devices, containing the first, second, three

IS is the p-bit registers, the first and second decoders, the first, second, third and fourth elements AND, the first and second groups of elements AND, the comparison circuit, the first element NOT at 20 than the inputs of the requested and the response address of the device are connected respectively to the inputs the first and second registers, the outputs of the first and second 3 registers are connected to the inputs of the second and second decoders, the outputs of the first and second elements And are connected to the first inputs of the And elements of the first and second groups, each output of the first decoder Not with the second inputs of the corresponding elements of the same name of the first and second groups, the outputs of the elements of the first and second groups are connected respectively to the first and second inputs of the same bits of the third register, the outputs of the third register trigger and the outputs of the second decoder are connected to the corresponding inputs comparison circuits, the output of which is connected to the first input of the third element AND, and through the first element NOT to the first input of the fourth. This AND, the polling input of the device is connected to the second inputs of the third and fourth elements AND, the outputs of which are the first and second outputs of the device exchange mode, the first and second inputs of the device mode setting are connected to the first inputs of the first and second AND elements, respectively, the second inputs which are connected to the device launch input, the fifth and sixth elements are entered AND, the third, fourth and fifth groups of the elements of I, the fourth n times the register, the second element NOT and the delay element, and the outputs of the fifth and sixth And are connected to the first inputs of the And elements of the third and fourth groups, the outputs of the first decoder are connected to the second inputs of the corresponding And elements of the third and fourth groups of the same name, and the outputs of the third and fourth elements of the third and fourth groups are connected respectively to the first and second inputs of the same name of the fourth register, the outputs of the triggers of the fourth register are connected to the first inputs of the elements of the same name And the fifth group, the outputs of the second decoder are connected to the second inputs of the corresponding dnoimennyh elements and the fifth group, the outputs of which are connected with the corresponding third inputs; third-trigger triggers of the same name, the third inputs of elements of And the fifth group are connected to the output of the delay element whose input is connected to the device polling input, the first input of the fifth element I is connected to the input of the sign of the device mode change and through the second element NOT to the first sixth input And, the second inputs of the fifth and sixth elements And are connected to the device start input. The drawing shows a block diagram of the device. The device contains input 1 of the requested address, input 2 of the response address, registers 3 and 4, decoders 5 and 6, groups of elements And 7-11, elements And 12-17, elements HE 18 and 19, registers 20 and 21, comparison circuits 22, delay element 23, inputs 24 and 25 for setting the mode, input 26 for the sign of changing the mode, input 27 for polling, outputs 28 and 29 for issuing the exchange mode, input 30 for the request. The device works as follows. When an external object is launched via bus 1, register 3 receives the address of this object. From the output of register 3, the address goes to a decoder 5, where the binary code of the address is converted to a position code. Each output of the decoder 5 is connected through the corresponding element And group 7 and the corresponding element And group 8 with the inputs of the corresponding trigger register 20, as well as through the corresponding element And group 9 and the corresponding element And group 10 with the inputs of the corresponding trigger register 21. Bus 24 or bus 25 a mode signal is received, and a trigger signal is received via bus 30. If the addressable external object permits a change in the exchange mode, then a signal of the mode change sign is sent via bus 26, otherwise this signal is not received. The mode signal and the signal of the change of the exchange mode are memorized in 5 bits of registers 20 and 21 corresponding to the excited output of the decoder, respectively. For definiteness, it is assumed that the unit state of the trigger of register 20 corresponds to the mode Write to an external object, and the zero state to the mode Read from an external object. When the external object (running) accepts the exchange request along with the address received on bus 2, the latter is stored in register 4. The signal from the exciter of the valuable decoder 6 enters the comparison circuit 22, which is compared with the state of the corresponding trigger of register 20 If this trigger register 20 is in unit state, then the output of the comparison circuit 22 is a high level, which is fed to the first input of the element 16 and the bus signal 28 is given a record mode signal. If the polled trigger register 20 is in zero match, the output of the comparison circuit 22 is low, and the output of the element 18 is NOT high. Consequently, with the appearance of the signal interrogation on bus 27 from the output of the element I) 7 on bus 29, a signal will be issued that determines the mode of reading. At the same time, the polling signal from bus 27 goes to delay element 23. From the output of delay element 23, this signal goes to the third inputs of elements of group 11, to the second input of one of the elements and which receives a signal from the excited decoder 6. If the trigger of the register 21 corresponds to the excited output decoder 6, is in the single state, then the signal from the output of the corresponding element AND of group 1 I is fed to the counting input of the corresponding trigger register 20. Consequently, the state of the corresponding trigger register ra 20 is reversed. With the arrival of the next polling signal on bus 27 from this external object, the mode signal is issued on another bus of the mode. If the corresponding trigger of register 21 is in the zero state, then the state of the corresponding trigger of register 20 does not change. With the arrival of the next polling signal on bus 27 from this external object, the mode signal is determined by the initial state of the corresponding trigger register 20.

The application of the invention allows to increase the speed of information exchange with external devices by changing the exchange mode without re-entering the address.

Claims (2)

1. Authors certificate of the USSR 309357, cl. G 06 F 13/06, 1971. 2. USSR author's certificate I-583422, KJi. G 06 F 3/04, 1977 (prototype).