SU1196883A1 - Information input device - Google Patents

Abstract

A DEVICE FOR INPUT OF INFORMATION, containing the first register, the comparison element, the decoder and the counter, the first input of which is. the input of the device, the outputs of the counter are connected to the inputs of the decoder and. the inputs of the first group of the comparison element, the inputs of the second group of which are connected to the outputs of the first register, the inputs of the group of which are the inputs of the first group of the device, characterized in that, in order to expand the field of application by providing the possibility of randomly changing the order of entering information frames in the computer, He introduced the second register, switch, trigger, first and second delay elements, the first counter input is connected to the second delay element input, the output of which is connected to the second trigger input, the output of which is the output of the device, the first input of the trigger is connected to the output of the switch, the inputs of the first group of which are connected to the outputs of the second register, the inputs of the group of which are the inputs of the second group S of the device, the inputs of the first and second (Lego registers connected to the output of the decoder, the outputs the counter is connected to the inputs of the second group of the switch, the output of the reference element is connected to the input of the first delay element, the output of which is connected to the second input of the counter. co O) CX) 00 co

Description

.

The invention relates to computing and. can be used to control the entry of data frames into a computer.

The aim of the invention is to expand the scope of application by providing the possibility of randomly changing the order of the input frame in the information in the computer,;. The drawing schematically shows the proposed device.

The device for entering information contains the first register 1, the comparison element, the decoder 3, the counter 4, the second register 5, the switch 6, the trigger 7, the first 8 and the second 9 delay elements, the first Yu and the second 1 groups of inputs, the input 12, the output 13.

The device works as follows.

When power is turned on, counter 4 and trigger 7 are zeroed. The decoder generates a signal, allowing the recording of information in registers 1 and 5.

For a group of 10 entries in register 1, the period n is recorded (the number of information frames in the group for which each information frame is allowed or denied entry into a computer). At the same time, a group of 11 entries in register 5 records a mask, a unit in the i-th (, ..., n) discharge of which means input permission, and zero means prohibition of entering the i-ro information frame of the group, i.e. (i-Hn-n) -ro information frame, in a computer.

Simultaneously with the issuance of the information frame from the external device, an input 12 is imparted with a gating pulse of the information frame. At the same time, the content of the counter is 4. increased by one, due to

9.68832

at the output of switch 6, the contents of the first register bit 5 appear. After the transients in counter 4

5 and the switch 6, the gating pulse of the information frame appears at the output of the delay element 9, resulting in the trigger 7 writing-. content of the first digit

10 of the register 5. The state of the trigger 7 is transmitted to the output 13. If there is a signal at the output 13, the input of the information frame into the computer is allowed, and in the absence it is prohibited.

15 Upon receipt of the next pulse Hi. the input 12 of the second mode. The counter 4 is incremented by one, and the trigger 7 records the contents of the next bit of register 5. The device operates in this way until the code for the number p is generated in the counter 4. When it enters the device to pair the last (pth) information

The 25th frame of the group. Value of the 5th bit of register 5 is recorded in trigger 7. In addition, the comparison element 2 generates a match signal of the contents of registers 1 and 5, which appears at the output of delay element 8 only after recording the contents of the nth bit yes register 5 to trigger 7. Counter 4 is zero, causing registers 1 and 5 to open for

,, record information. Therefore, while the counter 4 is in the zero state, approximately equal to the period of the information frames, the contents of the registers 1 and 5 can be changed.

In the future, the device operates as described above.

Claims (1)

DEVICE FOR INPUT INFORMATION, containing the first register, a comparison element, a decoder and a counter, the first input of which is. the input of the device, the outputs of the counter are connected to the inputs of the decoder and the inputs of the first group of the comparison element, the inputs of the second group of which are connected to the outputs of the first register, the inputs of the group of which are the inputs of the first group of the device, characterized in that, in order to expand the scope by allowing arbitrary changes in the order of input of information frames in the computer, it introduced a second register, switch, trigger, first and second delay elements, the first counter input is connected to the input of the second element and delays, the output of which is connected to the second input of the trigger, the output of which is the output of the device, the first input of the trigger is connected to the output of the switch, the inputs of the first group of which are connected to the outputs of the second register, the inputs of the group of which are inputs of the second group of the device, the inputs of the first and second registers connected to the output of the decoder, the outputs of the counter connected to the inputs of the second group of the switch, the output of the comparison element is connected to the input of the first delay element, the output of which is connected to the second input of the counter ika, "" SU "., 1196883