SU1517019A1 - Device for computing boolean functions - Google Patents

Abstract

The invention relates to automation and computing and is intended to implement Boolean functions. The purpose of the invention is to improve the performance of the device. The apparatus comprises a memory unit 1 constant, barring element 2, folded elements modulo two group 3 _.1 -3 _.N, N groups of elements 4 _.1 -4 _.N, an adder 5, the control unit 6, a register 7, a group of the argument inputs 8, the information output 9, the output of the sign of the end of operation 10 of the device, the clock input 11, the output of the sign of the end of the poll 12 of the memory block of constants 1. The values of variable weights, signs of weights and threshold value are recorded in the memory of constants 1. The code of the value of the weights is fed to the corresponding input I = of the element ADDITIONAL ON MODULE TWO (I = 1, N). If the weight code is zero, i.e. variable has a positive weight and at the corresponding input of the argument the signal is equal to logical one and at the corresponding input of the argument is equal to logical zero, then at the output of the I-th element CONSTITUTION ON THE MODULE TWO a single level signal is generated, coming to the inputs of the elements of the Groups. Accordingly, the binary weight code of the I-th variable enters the corresponding group of inputs of the adder 5. The latter generates a single signal at the transfer output if the sum of the weights of the bits of the input code is not less than the threshold value. 1 il.

Description

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with

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about

with

stant I, prohibition element 2, element group ADDITIONAL ON MODULE TWO, n groups of elements AND 4, -4, adder 5, control unit 6, register 7, input argument group 8, information output 9, output of the end of operation feature 10 device, a clock input 11, an output of a sign of the end of a poll 12 of a memory block of constants 1. The values of variable weights, signs of weights and a threshold value are recorded in the constant memory block 1. The code of the value of the weights is fed to the corresponding inputs of the group of elements AND, and the sign code of this weight is fed to the corresponding input of the i-ro element. If the weight code is zero, i.e. variable has a positive weight and at the corresponding input of the argument the signal is equal to logical one, or the weight code is equal to one and at the corresponding input of the argument the signal is logical zero, then the output of the i-ro element is COMPLETED BY MODULE TWO and a single level signal is generated. groups. Accordingly, the binary code of the weight of the Lth variable is fed to the corresponding group of inputs of the adder 5. Last

generates a single signal at the transfer output if the sum of the weights of the bits of the input code is not less than the threshold value. 1 il.

The invention relates to automation and computing, and is intended for the implementation of Boolean Functions in dp.

The purpose of the invention is to improve the performance of the device.

The drawing shows a block diagram of a device for calculating Boolean functions.

The device for calculating Boolean functions contains block 1 of constant memory, prohibition element 2, element group ADDITIONAL ON MODULE TWO 3, - 3, groups of elements AND 4-4, torus 5, control unit 6, register 7, argument group 8, format - output output 9, output 10 of the sign of the end of operation of the device, clock input I1 and output 12 of the sign of the end of polling of the constant memory block 1.

The implemented function is represented in a threshold-disjunctive form:

where Sgn is the threshold function symbol; S, -; - variable weight; Aj - threshold;

0

five

d

five

five

i. - a set of numbers of variables with negative weights;

| i - set of numbers of variables with positive weights.

At the same time, the weights of the variables uj,., Ui2 ;.

-W, - threshold A

, with signs of weights and value., the recording is made in the following order: the sign of the weight of the i-th variable equal to O for a positive weight and 1 for a negative weight, the binary code of the weight of the L-th variable (i 1, ..., n ), and after recording all weights of variables - the binary code of the threshold AJ 2 tIn addition, the realizable function can be represented in the threshold-conjunctive form: N p

y i Sgnfll tJ; i X; - A: 1

N

0

  Sgn J P

- (A

CJ., X;

L

goso ..

j; +) Sg I.T - f T

T

IU) .. J

A;

The information is recorded in the constant memory unit 1 in a similar manner.

When implementing a function by its threshold-disjunctive representation, the device operates as follows.

In the initial state, the output of control block 6 is a zero signal that permits the passage of clock pulses through prohibition element 2. At the clock input 11 of the device, clock pulses are applied. The clock pulse passes through the element 2 of the prohibition on the input of the read permission of the constant memory block J, from the output of which the codes recorded in the corresponding cells are read. The binary code of the weight of the i-th variable is fed to the first inputs of the elements And, and the code of its sign of the variable - to the first input of the i-ro element COMPLEX ON MODULE TWO 3; whose second input is the value of the variable x. From the i-ro input 8 of the argument through the register 7. At the same time, if the weight of the i-th variable is positive and its value equals a logical one, then at the output of the i-th element CONSTITUTION ON THE MODULE TWO, a single signal is generated that arrives at the second inputs of the corresponding elements AND 4 ,, Moreover, the binary code of the weight of the i-th variable comes from the outputs of the AND element to the i-th group of inputs of the adder 5. Similarly, if the weight of the i-th variable is negative and its value is logical zero, then the output of the i-th element is COMPLEX MODULE TWO

You devices, indicating the end of the work and the formation of the result, as well as the input element of the prohibition element 2, prohibit further passage of the clock pulses. The function value is read from the information output 9 of the device.

If after N cycles of operation of the device 10 at the output of the transfer of the adder 5 is not

the unit level signal is received, then when the N-pulse arrives from the clock input JJ at the output J2 of the polling end of the block 1 of the constant memory 15, a signal is generated that switches the control block 6 to the output. which appears a single signal, indicating the end of operation of the device, and a zero signal is removed from the information output 20 of the device 9.

In the case of the implementation of a function in its threshold-conjunctive representation, the operation of the device occurs in the same order. The difference is that if in any operation cycle of the device at the transfer output of the adder 5 a single level signal is not generated, then the control unit 6 of the control unit switches and the operation cycle ends. .

Thus, the device provides the formation of the result of not more than N cycles. The most efficient one arrives at the i-th group of in-, r effective is to use the devices of the adder 5. In the rest of the cases, when calculating a function from its

At the output of the corresponding element the CONDITION ON MODULE TWO - the zero signal and the code of the variable weight do not arrive at the corresponding input group of the adder 5, the data on the inputs is zero code. The (A + 1) -th group of inputs of the adder 5 from the outputs (n + 1) -and the group of the constant block 1 receives the code A 2. The adder 5 forms the sum of all j

3. A single signal and the weight code of the i-th pe-threshold-disjunctive representation are also formed, the disjunctive normal forms of which are quite complex, i.e. have a large number of simple implicants.

Claims (1)

Invention Formula g - d J (n + 1) received at its inputs binary codes. In this case, if the condition to; .. X, A., then a single signal is generated at the transfer output of the adder 5, otherwise it is zero. If the output of the transfer of the adder is 5 A device for calculating Boolean functions containing a memory block of constants and an element CONSTANT BY MODULE TWO, characterized in that, in order to increase performance, it contains (n-1) the element COMPONENT BY MODULE TWO (n is the number of variables of the function being implemented ), the element of the ban, n groups of elements And,. adder, control block and register, a single signal, this leads 55 informational inputs of which is connected to the operation of control unit 6, the output of which a single-level signal is generated, which arrives at the output 10 of the end sign for the device, the i-th output of the register (1 1, n) is connected to the first The input of the i-ro element is COMPLEX ON MODULE TWO, the second input is of the threshold-disjunctive representation, the disjunctive normal forms of which are quite complex, i.e. have a large number of simple implicants. Invention Formula j A device for calculating Boolean functions containing a memory block of constants and an element CONSTANT BY MODULE TWO, characterized in that, in order to increase performance, it contains (n-1) the element COMPONENT BY MODULE TWO (n is the number of variables of the function being implemented ), the element of the ban, n groups of elements And,. adder, control block and register, are not connected with the inputs of the device argument, the i-th output of the register (1 1, p) is connected to the first input of the i-ro element. CONSTITUTION ON A MODULE TWO, the second input is 15170 .9.g which is connected to the output of the sign of the weight of which is connected to the first input of the variable variable of the constant memory block, the house of the control unit, the second input of which the weight code is connected to the second is connected to the clock input with the first inputs of the elements And the i-device and the first input of the element groups, the second inputs of which are connected-ban, the second input of which is connected to the output of the i-ro element. COMPLEXING with the output of the sign of the end of work ON THE MODULE TWO groups, the outputs of the element device and the output of the control unit AND the i-th group are connected to the i-th, the third input of which is connected to the group of inputs of the adder, (n + 1) - d output of the adder and informational the group of inputs of which is connected to the output of the device, the output element the output of the threshold value 6jfoKa memory tapapit is connected to the resolution input constants, the output of the sign of the end of the reading of the block of memory constants.