SU1386985A1 - Data input device - Google Patents

Abstract

The invention relates to automation and computing and can be used in microprocessor complexes in the implementation of interrupt systems. The purpose of the invention is to increase the reliability of the input information. The device contains register 1, first 2 and second 6 blocks of bitwise comparison, element 3, group of elements 4, counter 6, trigger 7. The accuracy of the input information is increased by clocking the recording of information in the register and eliminating the hang of the circuit. 2 Il.

Description

(L

with

with

00 Oi

00 01

one

1386985

The invention relates to automation and computer technology and can be used in microprocessor complexes in the implementation of multi-level interrupt systems.

The purpose of the invention is to increase the reliability of the input information.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams of his work.

The device for entering information 10 (Fig. 1) contains a register 1, the first block 2 of bitwise comparison, the element AND 3, in the group of elements AND 4, the counter 5, the second lok 6 of bitwise comparison and the trigger 7. I The device works as follows .

which is fed to the first inputs of block 6. When the counter code exceeds the code on the second inputs of block 6, an interrupt signal is generated at its output. At the same time, the calculator at the input of the device sends a read signal, which is fed to the elements 4 and 4, and the information stored in register 1 is fed to the information outputs of the device. In this case, the counter 5 is reset and the interrupt signal disappears.

Claims (1)

Invention Formula A device for entering information containing a register, information inputs which are information inputs of the initial state of the device and the formatives of the device and connected to the inputs of the device’s input inputs are signals that are not measured by the group of the first block of 1 | (they are, as a result, at the output of register 1, the signals correspond to the input, at the output of locale 2 a low level, clock pulses- (| s do not change the state of the trigger 7.) When the signal changes at one of the Information inputs at the output of block 2 is a high level (Fig. 2), the collision through the element And 3 enters the information input of the register 7. On the first positive edge of the clock pulses of 25 doB, a positive edge is formed at the direct output of the trigger 7, which rewrites into the register 1 the changed input status, and one is added to counter 5 Regardless of the time of changing information at the device inputs, the output of the trigger 7 generates latching pulses (Fig. 2) with a double period of clock pulses, while the code at the output of the register comparison, the inputs of the second group of which are connected to the outputs of the register and With the first inputs of the group of elements AND, the outputs of co., which are informational outputs of the device, the second inputs of the group of elements of AND are the input of information reading and initial installation of the device, characterized in that, in order to increase the reliability of the input formations, an element I, a trigger, a second block of comparison, a counter, the first input of the element I is connected to the output of the first block of one bit comparison, and the second input with an inverse trigger output, the direct output of which is divine with clock inputs register and counter, the output element And is connected to the information input of the trigger, the clock input of which is the clock input of the device, the installation input in the "About counter  1 will not be equal to the input code. With e | g to the information input of the trigger c, is connected to the second inputs of the group ELECTRIC of block 2 receives a low level and the cops, the outputs of the counter are connected to The impulses of his state are not measured by the inputs of the first group of the second block, i.e. the unit returns to the initial discrete comparison, whose output is the output of the device ready output, the inputs of the second group of the second block at once The pulses from the direct output of the trigger 40 of the parallel comparison are the inputs of the set 7 counted by the counter 5, the output codes of the ready conditions of the device. which is fed to the first inputs of block 6. When the counter code exceeds the code on the second inputs of block 6, an interrupt signal is generated at its output. At the same time, the calculator at the input of the device sends a read signal, which is fed to the elements 4 and 4, and the information stored in register 1 is fed to the information outputs of the device. In this case, the counter 5 is reset and the interrupt signal disappears. Invention Formula devices and connected to the inputs of the first group of the first block Comparisons, the inputs of the second group of which are connected to the outputs of the register and the first inputs of the group of elements AND whose outputs are information outputs of the device, the second inputs of the group of elements AND are the input of information reading and initial installation of the device, characterized in that input information, the element I, the trigger, the second block of one bit comparison, the counter, where the first input of the element I is connected to the output of the first block of one bit comparison, and the second input with the input A trigger trigger output, the forward output of which is connected to the register and counter clock inputs, the output of the AND element is connected to the trigger information input, the clock input of which is the device clock input, the input of the counter