SU1084749A1 - Device for tolerance checking of pulse sequences - Google Patents

Abstract

A DEVICE FOR ADMISSION MONITORING OF PULSE SEQUENCES, containing the first OR element and the first delay element, the first and second code comparison schemes, the first code inputs of which are connected to the outputs of the upper tolerance register and the lower tolerance register of the memory block, respectively, and the second code inputs with the reverse output the counter, in which the inputs of the installation in the zero state of all bits, except the younger ones, are connected to the control input of the device, the element I, the output connected to the first output of the device, moves to the inverse and direct outputs of the first and second triggers, respectively, the installation inputs to the zero state are combined, and the counting inputs are connected to the outputs of the first and second code comparison circuits, respectively, in order to expand its functionality the account for ensuring the tolerance control of sequences of pulses, which is defined non-monotonically changing; with a parameter, the second delay element and the second OR element, whose output is connected to the subtracting input of the reversible counter, are entered into the device, the first input - with the output of the second delay element, and the second input - with the first, information input of the device and with the input of the second delay element, the output of the first (L of the OR element is connected to the sum of the 11 m input of the reversible counter, the first input with the output of the first delay § element, and the second input with the second information input of the device and the input of the first delay element, second and third device outputs connected respectively to the eo nym direct output of the first flip-flop and an inverted output of the second flip-flop, setting inputs to the zero state trigge4 jpoB connected to the control input of the device and installation into a single entry; on-border state of the least significant bit down counter.

Description

The invention relates to automation and computer technology and can be used in the implementation of technical means of digital instrumentation systems and automatic control devices. A device for comparing binary numbers with tolerances is known, comprising a counter, triggers, AND, OR, NOT, pulse shaper, elements comparisons and memory blocks ij. The disadvantages of this device are its small functional capabilities, since the device allows you to control only completely stable values and does not allow.-Et to maintain tolerance control over the sequence of pulses that determine non-monotonically changing parameter, i.e. when the monitored parameter repeatedly enters and leaves the tolerance zone. : The closest in technical essence to the present invention is a digital comparator comprising a reversible counter, a memory block having upper and lower tolerance registers, code comparison circuits, triggers, AND elements, OR element and delay element, and the information input of the device is connected with the counter input of the counter, the output of which is connected to the first inputs of the first and second Kodo comparison circuits; the first and second outputs of the memory unit. Connected to the second inputs of the first and second comparison circuits of the codes, respectively, the outputs of which They are connected to the counting inputs of the first and second triggers, respectively, C2. The known device also cannot maintain tolerance control over the sequence of pulses determining the non-monotonically varying parameter. This is due to the fact that the switching of triggers, the state of which is determined by the position of the parameter value relative to the tolerances, occurs when the parameter value coincides with one of the tolerances. Therefore, switching of triggers can occur when the value of a parameter reaches the limit of the tolerance field, not its transition. For example, if the lower tolerance is equal to three, if the parameter changes as 1, 2, 3, 2, a false re-49 will occur. 2 the trigger is turned on and the last parameter value is incorrectly fixed as falling into the tolerance field. The purpose of the invention is to expand the functionality by providing tolerance control of pulse sequences defining non-monotonically varying parameter. The goal is achieved by the fact that the device for tolerance control is sequential (pulse pulses containing the first OR element and the first delay element, the first and second code comparison schemes, the inputs of the first code of which are connected to the outputs of the upper tolerance register and the lower tolerance register of the memory block respectively, and the inputs of the second code are with the output of the reversible counter, in which the inputs of the installation in the zero state of all bits, except the younger one, are connected to the control input of the device, the AND element and the output terminal Adjusted to the first output of the device, inputs to the inverse and direct outputs of the first and second flip-flops, respectively, the installation inputs in the zero state of which are combined, and the counting inputs connected to the outputs of the first and second code comparison circuits, respectively, the second delay element and the second OR element are entered whose output is connected to the subtracting input of the reversible counter, the first input is from the tricks of the second delay element, and the second input is connected to the first information input of the device and to the input of the second delay element, with this output of the first element OR is connected to the summing input of the reversible counter, the first input - with the output of the first delay element, and. the second input — with the second information input of the device and the input of the first delay element; the second and third outputs of the device are connected respectively to the direct output of the first trigger and the inverse output of the second trigger; the installation inputs to the zero state of the trigger are connected to the control input of the device and the installation input unit state of the low-order reversible counter. The drawing shows a diagram of a predictable device.

The device contains a reversible counter 1, a block of 2 frames, circuits 3 and 4 comparison codes and triggers 5 and 6 element AND 7, elements OR 8 and 9, delay elements 10 and 11, information inputs 12 and 13, control input 14, outputs 15 -17.

Memory block 2 contains upper and lower tolerance registers.

The device works as follows. ,

Before starting operation, a signal is sent to control input 14, which sets the triggers 5 and 6 to the zero state, and the number 1 is written to counter 1. In memory block 2, the upper and lower LO values are stored, which are respectively the inputs of circuits 3 and 4 of the comparison codes with a shift by one bit towards the higher bits, which is equivalent to multiplying the tolerance value by two.

The signal of an increase in the value of the parameter by one is fed to information input 12, and about decreasing, to input 13.

The circuit from the delay element 10 (11) and the OR element 8 (9) when a signal arrives at information input 12 (13) generates two pulses that arrive at the summing (subtraction) input of the reversing counter 1, therefore

KC 2K „+ 1,

where Kg is the code in counter 1, Kf is the actual value of the parameter, i.e. Kj. - odd number . And since the tolerance codes arriving at the inputs of the comparison circuits 3 and 4 from the memory block 2 are always even, then at the local extremum points, two comparisons of the comparison circuit 3 I4 will occur. Thus, in the above 5 example, the double value of the lower tolerance is received from memory block 2, i.e. 6, and the contents of counter j are changed as follows: 1, 2, 3, 4,

to 5, 6, 7, 6, 5, this will result in two operations of the code 4 comparison circuit 4 (if the inputs to its code inputs coincide) and two triggers of the trigger 6 and the

15 children correctly fixed that the last parameter value is less than the tolerance.

When the parameter value passes through the lower tolerance (regardless of

0 of the direction of change of the parameter) the comparison circuit 4 is triggered and the trigger 6 is switched, and when the parameter value passes through the upper tolerance, the comparison circuit 3

5 codes and trigger 5. The signals at the outputs 16 and 17 of the device mean that the value of the monitored parameter is greater and less than the tolerance, the signal at the output 15 15 that the value of the monitored parameter is within the tolerance field.

The positive effect of using the invention is to

5 implementation of the possibility of tolerance control of a sequence of pulses determining a non-monotonically varying parameter, which expands the functionality and scope

0 device application.

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Claims (1)

DEVICE FOR ACCESS CONTROL OF PULSE SEQUENCES, containing the first OR element and the first delay element, the first and second code comparison circuits, the first code inputs of which are connected to the outputs of the upper tolerance register and lower tolerance register of the memory block, respectively, and the inputs of the second code are connected to the output of the reverse counter in which the inputs of the installation in the zero state of all digits, except the lowest, are connected to the control input of the device, the element And, the output connected to the per-; the device’s output, the inputs to the inverse and direct outputs of the first and second triggers, respectively, whose input to the zero state are combined, and the counting inputs are connected to the outputs of the first and second codes comparison circuits, respectively, characterized in that, in order to expand its functionality beyond the account of the admission control of the pulse sequences, I determine prnth non-monotonously changing -; . parameter, the second delay element and the second OR element are introduced into the device, the output of which is connected to the subtracting input of the reverse counter, the first input is the output of the second delay element, and the second input is with the first, information input of the device and with the input of the second delay element, the output of the first OR element is connected to the summing input of the reverse counter, the first input to the output of the first delay element, and the second input to the second information input of the device and the input of the first delay element, the second and third outputs roystva connected respectively to the direct output of the first flip-flop and an inverted output of the second flip-flop, inputs of flip-flops in the null state are connected to a control input of the input device and setting the state of a single LSB down counter. SU 1084749