SU1287287A1 - Shift-to-digital converter - Google Patents

Abstract

The invention relates to automation and computing, can be used in digital position controllers, information systems, mechanisms for controlling the position of mechanisms. The aim of the invention is to increase the reliability of the transmitted information by the converter. For this, the displacement transducer in the code containing coding element 1, sensitive elements 2, transducer 3 codes, register 4 and the element OR-NOT 7, code control block 5, the control pulse driver 6, the D-trigger 8 and the element OR are entered 9. The goal is achieved due to the fact that, together with the code transmitted to the consumer, the Ready and Disable signals are generated, which prohibit the reading of the code from the converter outputs in the presence of an encoding and conversion error, as well as during transients in the circuit x converter and telecommunication lines. I zp f-ly, 4 ill. (/)

Description

The invention relates to automation and computer technology and can be used in digital position controllers, information systems, and position control systems.

The purpose of the invention is to increase the reliability of the transmitted information by the converter.

FIG. 1 is a diagram of a displacement converter to parallel code; in fig. 2 - diagram of the pulse shaper; FIG. 3 shows a control pulse driver circuit; in fig. 4 shows an example of execution of a code control block for twelve bits.

The displacement transducer to the code contains the coding element 1, the block of 2 sensitive elements, the transducer 3 of the code, the register 4, the block 5 of the control code, the driver 6 of the control pulses, the element OR-NOT 7, the D-flip-flop 8, the element OR 9

Shaper 6 control pulses contains an element EXCLUSIVE OR 10, pending multivibrators 11 and 12, a resistor 13, a capacitor 14.

The code control unit 5 contains the elements EXCLUSIVE OR 15-26, the current-limiting element on the resistor 27 and the key 28. The control pulse shaper 6 has outputs 29-31.

The Converter operates as follows.

Moving the coding element

1 calls the triggering of the sensitive elements of block 2, which read the information and transmit it to the inputs of the converter 3 of the code. The change in the signal level at the output of the first discharge of the sensitive elements of the block

2 involves the beginning of the process of switching the elements of the converter 3 of the code in accordance with the chosen method of converting a double brush or V-reading and forming a movement code at its outputs, respectively at the inputs of the register 4 and the block

5 control code. Changing the code at the output of converter 3 of the code causes the operation of the elements of block 5 of the control code.

0

t5

20

25

87287-2

(t - t,) and;) Outputs 29 - 31 formers 6 utgras of pulses, with t.-r,,.

In the initial state at the outputs 29-31 of the driver 6, the control pulses have a low signal level, the output of control unit 5 of the k-ode is a high signal level, the output of the OR-HE element 7 is low signal level, the output of the Converter readiness is high signal level, corresponding to reliable information at the outputs of register 4, at the first and second inputs of the elements OR 9 and at the output of the Converter Inhibit, low levels of signals are set.

If in the intervals between the appearance of the pulses at the output 29 of the driver 6 of the control pulses at the output of the code control unit 5 for any reason, the signal level changed to low, then the output of the OR-NOT 7 element, respectively, at the R input of D- trigger 8, a high signal level is set, as a result, at the output of the Converter readiness, a low signal level is set, corresponding to the unavailability of the driver, due to the appearance of a read error. At the same time, at the second input of the element OR 9 and at the output of the Converter Inhibit, high levels of signals are set. High output signal A converter in this case prohibits reading information from the outputs of register 4 due to the unreliability of the code at the output of register 4, which is determined by the low level at the output of the Ready transducer.

The change of the code at the output of the converter 3 of the code is accompanied by transients in the elements of the converter 3 of the code and block 5 of the code control, and during V-reading this process is longer. To exclude the recording of the signal from the output of block 5 of the control code in the D-flip-flop 8 at the time of transients when changing the code, the element OR-NOT 7 is introduced.

thirty

35

45

50

The change in the signal level of the first bit at the output of the converter 3 of the code causes the appearance of three pulses (Fig. 2) of different duration

The pulse from the output 29 of the former 6 sets the output level of the element OR NOT 7 to a low signal level regardless of the signal level on the second

3

the input is OR-NOT 7. Thus, the duration of the signal from the output 29 of the driver 6 pulses should be no less than the transit time in the elements of the converter 3 codes and the control unit 5. The pulse from the output of the driver 29, 6 pulses with its leading edge confirms or sets the output of the converter to a high signal level, if the R-input of the D-flip-flop 8 is a low signal level. If the output of block 5 of the control code has a low signal level, respectively, a high signal level at the R input of D-flip-flop 8, then a high signal level setting at the output of the converter does not occur on the leading edge of the pulse From the output 29 of the driver 6 pulses, due to priority R-inputs of D-flip-flop 8 with respect to its other inputs. The level of the signal at the R-input of the D-flip-flop 8, which is set by the pulse from the output 29 of the driver 6 at the transient time in the converter 3 of the code and the code control unit 5 through the element OR-HE 7, is delayed by the element 11ПИ-НЕ 7 at the time of the transitions in the OR-NOT 7 element itself. Thus, the leading edge of this pulse arrives at the C input of the D flip-flop C a little earlier. The signal level at the R input of the D flip-flop 8 changes and, as a result, the possibility of flashing a low signal at the output is eliminated. .

The impulse from the output 30 forms

At the time t (Fig. 2), l 6 writes to the register 4 of the code established at its inputs. The duration of this pulse is selected taking into account transients in the communication lines and the response time of the consumer information system, but no less.

The pulse from the output 31 of the pulse builder 5 is fed to the first input of the element OR 9, at the output of which the prohibition signal is generated, prohibiting the reading of the code from the outputs of register 4 for a time (. The pulse duration is selected from the condition that the time interval is not less than the transient time the code for the outputs of register 4.

5 tO 5 0 5

0

five

The code control unit 5 works as follows.

If the total number of bits of the movement code and additional bit at which the high signal level is set is even, then a high signal level is set at the output of the code control unit 5. Odd parity is possible with the appropriate coding of the additional bit Extra. with simultaneous connection to a low signal source (General O). In this case, if there is a reliable code, a high signal level is established at its output.

As a result of a malfunction of the converter in any of the bits, including the control, the output of the code control unit 5 sets a low signal level corresponding to the invalid code at the inputs of the code control unit 5 and register 4.

Claims (2)

Invention Formula 5 tO 5 0 5 0 five 0 one A motion converter in a code containing a serially connected coding element, a block of sensing elements and a code converter, the outputs of which are connected to the inputs of the register, the outputs of which are the outputs of the converter, a KPI-NOT element, characterized in that by increasing the reliability of the output code, a code control block, a control pulse driver, D trigger and an OR element are entered into it, the code converter outputs are connected to the inputs the control unit code, the output of which is connected to the first input of the element OR NOT, the output of which is connected to the R-input of the D-flip-flop, the first output of which is the output of the Converter, the second output is connected to the first input of the OR element, the output of which is the output of the converter Inhibit, the output of the lower digit of the code converter is connected to the input of the control pulse generator, the first output of which is connected to the second input of the OR element and the C input of the D-flip-flop, the second output to the second input of the OR element, 5 1 the third output is with the register entry input, the D input of the D flip-flop is connected to the signal unit bus. 2. Converter according to claim 1, characterized in that the code control block contains six elements EXCLUSIVE OR of the first group, three elements EXCLUSIVE OR of the second group, two elements EXCLUSIVE OR of the third group and the element EXCLUSIVE OR, key and current limiting element, inputs of the elements EXCLUSIVE ILI The first group are the inputs of the code control block, the outputs of each pair of EXCLUSIVE OR elements. the first group is connected to the entrance 287287 -6 of the corresponding elements of the EXCITING ORIGINAL OR of the second group, the outputs of the first and second elements of the EXCLUSIVE OR of the second group are connected to 5 inputs of the first element EXCLUSIVE OR the third group, the output of the third element EXCLUSIVE OR the second group is connected to the first input of the second element EXCLUSIVE OR the third Group 0, the second input of which is connected through the current limiting element to the power bus and through the key to the common bus, the outputs of the EXCLUSIVE OR elements of the third group are connected  5 with the element inputs EXCLUSIVE OR, the output of which is the output of the code control block. and. Ub -fV t / -fV fig.Z SL L P P HL P Phase 2 eleven AT 12 IL 2p 15 5p 6p 17 n rOO 2b . one 2if