SU1084856A1 - Device for receiving commands - Google Patents

Abstract

1. DEVICE FOR RECEIVING KMAND, containing a block of delay elements, the first output of which is connected through the clock code group selector to the first trigger input, the second output of the block of delay elements is connected to the input of the first working code group selector, a signal converter containing a pulse generator, the output of which is connected with the first input of an element whose output is connected to the first input of a pulse counter, a command decoder whose output is the output of a signal converter and a device whose input It is the input of a block of delay elements, the first and second outputs of the trigger are connected respectively to the second inputs of the AND element and the pulse counter of the signal converter, characterized in that, in order to increase the noise immunity of the device, additional workgroup selectors are introduced into it, and the total number of selectors working code group K is within 0.5 (n + 1) 4 K4n - 1, where n is the number of pulses in the code and the logic block, the additional second outputs of the block of delay elements are connected to the inputs corresponding to additional working selectors of the code group}, the outputs of the selectors of the working code group are connected respectively to the first inputs of the logic block, to the second input of which the output of the selector of the clock code group is connected, the key block, the decoder of the end of the working cycle, the command register, the output of which is connected to the signal converter with the first input of the command decoder, the output of the pulse counter is connected to the input of the decoder of the end of the working cycle and to the first input of the key block, the output of which is connected to the input the command register, the output of the decoder of the end of the working cycle is connected to the second inputs of the command decoder and the trigger, the output of the logic block is connected to the second input of the key block of the signal converter.

Description

2. The device according to claim 1, characterized in that the logic block contains triggers, elements AND and the element OR, the output of each trigger is connected to the corresponding inputs of the element of the same name And and each subsequent element And, the output of each element And is connected to the corresponding input of the element OR, the output of which is the output of the logic block, the first input of which is the first inputs of the flip-flops, the second inputs of the paddle block are the second inputs of the flip-flops and the corresponding inputs of the elements I.

The invention relates to a technique for transmitting electrical signals and is intended for receiving commands transmitted by signals: time-pulse modulation, pulse-time codes (VIM - VCI).

Radio control systems are known for transmitting commands that use VIM - VCI signals, by which a command is transmitted as a time interval between a clock and a working code group of the VCI, and a device for receiving commands of the VIM - VCI contains a decoder of the VCI of the clock and working code group and demodule the VIM torus, which converts the time interval between the clock and working code groups into a received command.

And the closest to the proposed is a device for receiving commands containing a block of delay elements, the first output of which is connected via a clock selector to the first trigger input, a second output of a block of delay elements connected to the input of the first information signal selector, a signal converter containing a pulse generator, output which is connected to the first input of the element And whose output is connected to the first input of the pulse counter, the decoder of the information signal, the output of which is the output The sigpal converter and the device, whose input is the input of the block of delay elements, the first and second outputs of the trigger are connected respectively to the second inputs of the And element to the pulse counter of the signal converter 2.

The disadvantage is that the device has a low level of immunity because, under interference conditions, due to the suppression of true and the appearance of spurious pulses at the input of the delay line, the working code group is selected at the receiving point not at the proper, but at an arbitrary random time, caused by interference , which leads to a distortion of the command.

The purpose of the invention is to increase the noise immunity of command reception.

The goal is achieved by the fact that in the device for receiving commands, containing a block of delay elements.

the output of which is connected through the clock code group selector to the first input of the trigger, the second output of the block of delay elements is connected to the input of the first selector of the working code group, a signal converter containing a pulse generator, the output of which is connected to the first input of the And element whose output is connected to the first input of the counter pulses, a command decoder, the output of which is the output of a signal converter and a device whose input is an input of a block of delay elements, first and second outputs of a trigger connected respectively to the second inputs of the element And and

pulse counter of the signal converter, additional selectors of the working code group were entered. The total number of selectors of the working code group K is within 0.5 (n -f) K n - 1, where n is the number of pulses in the code and the logic block,

additional second outputs of the block of delay elements are connected to the inputs of the corresponding additional selectors of the working code group, the outputs of the selectors of the working code group are connected respectively to the first inputs of the logic block, to the second input of which the output of the clock code group selector is connected, the key block, the decoder of the working end are entered into the signal converter tact, the command register, the output of which is connected to

d the first input of the command decoder, the output of the pulse counter is connected to the input of the decoder of the end of the working clock and to the first input of the key block whose output is connected to the input of the command register, the output of the decoder of the end of the working clock of the second command decoder and trigger, output logic block is connected to the second input of the key block of the signal converter.

In addition, the logic block contains a trigger ;, the AND elements and the OR element, the output of each trigger is connected to the corresponding inputs of the AND element name of the same name and each subsequent AND element, the output of each AND element is connected to the corresponding input of the OR element, the output of which is the output of the logic block The first input of which are the first inputs of the flip-flops, the second inputs of the logic block are the second inputs of the flip-flops and the corresponding inputs of the elements I. In FIG. 1 shows a block diagram of a device for receiving commands; in fig. 2 shows a possible execution of a logical block. The device consists of a block of 1 delay elements, a selector 2 of a clock code group, selectors 3 of a working code group, trigger 4, a signal converter 5, which includes a generator of 6 pulses, element 7, a counter of 8 pulses, a decoder of 9 commands, block 10 keys, the register of 11 teams and the decoder 12 end of the working cycle. Logic block 13 contains triggers 14 - 1-%, elements AND, element OR 16. Selectors 3 are made, for example, in the form of logical threshold elements with a digital threshold i-ro selector r p + i, i iTR, where K is the total the number of selectors 3. The key block 10 contains M keys (where M is the number of register bits 11 commands), the inputs and outputs of which are the information inputs and outputs of the block, and the control inputs of all the keys are connected to the common control input of the block to which no census signal is received. With the help of K selectors of the working code group, the moments of occurrence of all true or false working code groups with the number of pulses from n to n - k + 1 are recorded and output to the logical block. The logical block generates a signal to allow the rewrite of the number in the signal converter from the pulse counter to register only in the event that the repeated signal of fixation of the working code group came from the selector with a higher threshold than the previous one. Therefore, in the register, by the end of the working cycle, this command is stored, which corresponds to the moment of fixation of the working code group with the greatest number of pulses. As shown by the noise immunity calculations, which are given below, this gives noise gains in terms of noise immunity in the order of 3 dB compared with the known device containing one selector of the working code group. The device works as follows. At the moment when the clock code group arrives at the inputs of the selector 2 through the block 1 of the delay elements, the signal from the output of the selector 2 turns on the trigger 4 and the converter 5 starts working, in which the counting pulses from the generator 6 go through the element 7 to the counter 8. at the time of the arrival of the working code group, true or false, from one of the selectors 3 through the logic block 13 a pulse arrives at the third input of the converter 5 and then at block 10; on this impulse. The current number of states of counter 8, corresponding to the moment of fixation of the working code group, is transferred from counter 8 to command register 11. Logic block 13 generates a second census pulse to block 10 only if a second work group fix signal comes from the work group selector 3 with a higher threshold than the selector from which the previous work code group received signal. For this, the logic unit 13 is made, for example, in the form of a register containing K flip-flops 14 with AND 15 elements connected to them and an OR 16 element whose output is the output of a block connected as shown in FIG. 2. When a selected signal from the output of one of the selectors 3 arrives, the trigger cell of the same name is triggered in block 13, the signal from the output of which prevents the OR element from passing 16 signals from the outputs of the selectors with a lower threshold and from the output of this selector. The trigger 14 of the block 13 is zeroed at the beginning of each work cycle with a pulse from the selector 2. Thanks to such work of the logic block 13, in the command register 11, the command that corresponds to the fixing time of the working code group with the largest number of pulses is recorded at the end of the working clock. Reading the command from register 11, via the decoder 9 commands and the first output of the converter is performed at the moment of the end of the working clock, determined by the decoder 12 of the end of the working clock according to the corresponding state of the counter 8; at the same time, trigger 4 is switched to the stop state via another output of the converter, and counter 8 turns off with a signal from the output of trigger 4. After the next clock code group arrives, the process repeats and the next command is issued to the output of the converter. As is known, the probability of an erroneous reception of a command transmitted by VIM-IVK signals when using one selector of a working code group (i.e., in a known device) is / Qi5jia 4 Rosh.1-gmtp-1 s ;; Chr (-and ) (i) where m1 is the number of pulses of the VCI of the working code group; CL is the relative energy (signal-to-noise ratio) of a single CPI pulse; t is the number of teams (VIM positions) in one working cycle. In this case, the optimal logical threshold of the selector working code group Copt 0.5 p.

Claims (2)

1. A device for receiving commands containing a block of delay elements, the first output of which is connected through a clock code group selector to the first input of the trigger, the second output of the delay element block is connected to the input of the first selector of the working code group, a signal converter containing a pulse generator, the output of which is connected with the first input of the And element, the output of which is connected to the first input of the pulse counter, a command decoder whose output is the output of the signal converter and the device whose input is is the input of the block of delay elements, the first and second outputs of the trigger are connected respectively to the second inputs of the element And and the pulse counter of the signal converter, characterized in that, in order to increase the noise immunity of the device, additional selectors of the working code group are introduced into it, and the total number of selectors of the working code group group K lies within '[0.5 (n + 1)] 4 K 4 η - 1, where η is the number of pulses in the code and the logic block, additional second outputs of the block of delay elements are connected to the inputs of the corresponding additional selectors of the working code group, the outputs of the selectors of the working code group are connected respectively to the first inputs of the logic block, to the second input of which the output of the selector of the clock code group is connected, a key block, a decoder of the end of the working clock, a command register, the output of which is connected “Dinen with the first input of the command decoder, the output of the pulse counter is connected to the input of the decoder of the end of the clock cycle and to the first input of the key block, the output of which is connected to the register input to Omand, the output of the decoder of the end of the clock cycle is connected to the second inputs of the command decoder and the trigger, the output of the logic block is connected to the second input of the key block of the signal converter. Figure 1 2. The device according to π. 1, characterized in that the logic unit contains triggers, AND elements, and an OR element, the output of each trigger is connected to the corresponding inputs of the same element AND, and each subsequent element AND, the output of each AND element is connected to the corresponding input of the OR element, the output of which is the output of the logical block, the first input of which is the first inputs of the triggers, the second inputs of the logical block are the second inputs of the triggers and the corresponding inputs of the elements I.