SU1385309A1 - Device for receiving 3-time-repeated control commands - Google Patents

Abstract

This invention relates to remote control. The purpose of the invention is to improve the noise immunity of receiving control commands. The device contains .block 1 of the memory elements of the input information, the majority block 2. block 3 keys, analyzer 4 code feature, shift register 5, decoder 6, block 7 elements OR, counters 8, 9 and 16 pulses, elements OR 10 and 12, element II, dispenser 15 pulses. The device includes a comparison block 13, a memory of the reference combination 14, counters 17 and 18 named after them: pulses, decoders 19, 22 and 23, element OR 20, RS-flip-flops 21, 24 and 25, elements 26 and 27, the element 28 and the key 29. The device receives three repetitions of the control command, in which the selection of the phase start combination is performed by counting the number of the received phase trigger combinations of the three repetitions of the command with the reference phase start combination HU1X. The reception of the information part of the control command is performed by majority summing up the elements of the information parts of the three repetitions of the command. This prevents the possibility of false reception of a transformed control command. 2 Il. S O)

Description

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The invention of the command post for telecontrol and can be used to receive three-times non-repairable control commands containing a combination of phase start and E11 (} and a part of the game.

The aim of the invention is to improve the noise immunity of receiving control commands.

FIG. a structural electrical circuit of the proposed device for receiving triple-repeated control commands is presented; pas figs. 2 is a timing diagram of the signals explaining the operation of the device for receiving triple-repeatable control commands.

A device for receiving triply repeated control commands contains a block I of memory elements of input information, a majority block 2, a block 3 of keys, a code character analyzer 4, a shift register 5, a decoder 6, a block 7 of OR elements, the first and second counters 8 n 9 of pulses , first element OR 10, element I I 1, second element OR 12, comparison unit 13, memory block 14 of the reference combination, pulse distributor 15, third pulse counter 16, first and second additional counters 17 and 18 pulses, first additional decoder 19 complement ln element OR 20, first RS-flip-flop 21, second and third additional decoders 22 and 23, second and third RS-flip-flops 24 and 25, first and second additional elements And 26 and 27, element 28, additional key 29..

The input memory unit 1 contains the first, second and third memory blocks 30-32. Block 3 of the keys contains the first and second keys 33 and 34 and the call-in element 35. Block 7 of the OR elements contains the first, second and third elements OR 36-38.

A device for receiving triple-repeatable control commands operates as follows.

A short clock pulse arriving at a reception frequency F (Fig. 2a) at a clock input of a device for receiving three times repeated control commands (Fig. I) sets the first state of the distributor 15, switches the first, second and third waves for a short time. blocks 30-32 of memory from read mode to write mode. This ensures that the input (received) symbol is written to the corresponding first, second or third block (30-32) of the unit, the choice of which is determined by the state of the second counter 9. The counting input of the second counter 9 receives a signal from the high-order output the first counter 8. The signal from the output of the second counter 9 through the first, second or third elements OR 36-38 is fed to the input selection of the memory cell corresponding to the first, second

or the third memory block (30-32), and the signals arriving at the address inputs of the first, second and third memory blocks 30-32, are determined by the state of the first counter 8. After the recording is finished, the frequency pulse F through the first element OR 10 measurement (em on "T state of the first counter 8.

Subsequently, pulses are received at the counting input of the third counter 16 through the AND 11 element and the counting input of the first, counter 8, through the first element OR 10 and the AI element, from the ratio, where P is the receive frequency; n is the number of elements of the coding combination of the control command.

After counting n pulses from the output of the third counter 16, the second additional decoder 22 sends a signal to the clock input of the distributor 15 (Fig. 2 g), which switches the distributor 15 to the second, third and fourth states in sequence. The signals of the first, second and third outputs of the distributor 15 are shown in FIG. 2d, d, e, respectively.

5 When installing the distributor 15 to the fourth state, the signal (Fig. 2d) from the first output of the distributor 15 enters the first input of the element 11 and prohibits the passage of the processing frequency pulses through it. Pulse resolution

0 processing takes place after the initial state of the distributor 15 is set by a reception frequency F pulse. Thus, the formation of a packet of 3 pulses (Fig. 26) is used, which are used to read 3 3 bits of information from the first, second, and third memory blocks 30-32.

Let during the recording of the next bit of information, the i-th address is selected by the first counter 8, and the second memory block 31 is selected by the second counter 9 through the second OR 37 element. After just recording the information symbol, in the i-th memory cell of the second memory block 31, the first counter 8 is set to i-f-J. If the last memory cell is written in the i-th cell

5, the symbol of the third command repetition, then in the i-f 1st cell the first character of the first repetition of the command recorded 3 n times ago is found; This symbol is supplied first to the output of the second memory block 31. Further receipt of processing pulses at the input of the first counter 8 sequentially selects i + 2, ..., the n-th address of the second memory block 31.

Each time after selecting the nth address, the state of the second counter 9 is switched.

I and, through the respective first, second and third elements OR 36-38, select the next one from the first, second and third blocks 30-32. After the pulses arrive at the 3p output, the first counter 8 is in the 1 + 1 address selection state, and

the second counter 8 is in the state of selecting the second memory block 31. As a result, sequential recording of newly received information and sequential reading of received information is provided. In doing so, the oldest bit of information is read first, and the bit just recorded is read last.

By forming a pulse train (FIG. 26), the third counter 16 (p) at each reception cycle starts counting from the first state and, successively changing the state of the inputs of memory block 14 of the reference combination, reads the reference phase-start combination, which goes to block 13 compare. The comparison unit 13 also receives information read from the first, second and third memory blocks 30-32.

The signals from the outputs of the second additional decoder 22 control the state of the second RS flip-flop 24. At the forward output of the second RS flip-flop 24, a control signal is generated (Fig. 2c), which switches the device to receive triple-repeated control commands for analyzing the phase-start combination (level "1 in Fig. 2c) or analysis of the information part of the management team (level" O in Fig. 2c). The signal about the mismatch of the reference combination of the phase start and the received information from the output of the comparator unit 13 goes to the counting inputs of the first and second additional counters 17 and 18. The second additional counter 18 is reset to "O signal from the second RS flip-flop 24, which acts during the analysis of information elements of a comma. If during the action of the signal "1" (Fig. 2c) not a single pulse arrives at the counting input of the second additional counter 18, the third RS flip-flop 25 will remain in the initial state at the second, first and third inputs of the second additional third element And 27 permitting signals from the output of the distributor 15 (Fig. 2e) of the direct output of the third RS flip-flop 25 and the output of the HE element 28. match. The output signal of the second additional element I 27 goes to the control input of the second key 34, which closes and passes information elements command read from the first, second and third memory blocks 30-32 to the information inputs of the analyzer 4 and register 5. Through the additional key 29 closed by a command from the output of the NOT element 28, frequency f pulses go to the counting input of the analyzer 4 and register 5. If the encoding law is as specified, the analyzer

4 generates a decryption enable signal that arrives at the decoder 6 and enables decryption of the received control command. Thus, a simple reception of information is carried out. If, when reading information from the first, second and third memory blocks 30-32 from comparison unit 13, a signal is received that the reference and received elements of the phase start do not match, the signal from the second additional counter 18 (from the output

- the low-order bit) switches the third RS flip-flop 25 to the state "1", which leads to a second key 34 and further to the impossibility of simply receiving information elements.

5 If during the comparison of the elements of the phase start of three repetitions with the reference, the first additional counter 17 has a number greater than K, then through the first additional decoder 19 and the additional element OR 20 to the S input

0, the first RS flip-flop 21 does not receive a pulse and for the majority reading from the first, second and third memory blocks 30-32 of information elements of all three repetitions, the signal from the output of the first additional element 26 (Fig. 2h) closes the first key 33. The information inputs of the analyzer 4 and register 5 receive the command information symbols, while the majority block 2 produces the majority addition of the same-named bits.

0 all reps. Further, the command is received and decrypted as described, and the first additional counter 17 is reset to " O with a short pulse of receiving frequency F. As a result, the informational part of the majority-sum management command is reordered.

The K number is chosen such that the maximum likelihood of receiving a phase start combination is ensured.

0 with a lower probability than a simple reception of a false selection of a phase-start combination from noise. If random code combinations of length m characters that are not phase-start combinations are analyzed, then the average

five

the number of mismatches tends to be in the limit to the value, and K must meet the condition K f-3-. At the same time, if in the first, second and third blocks 30-32 of memory 0 there are not three, but only two repetitions of a command or one of three repetitions strongly distorted by the grouped noise, then the number of discrepancies in the analysis of the phasing combination may be less than K. The conduct of the majority processing of information in this case is inexpedient, since this can lead to a false reception of t | unmasked team.

Therefore, a second lower threshold is provided, which prohibits major analysis of the information part of the management team until all three repetitions of commands 1e1 are in the first, second, and third memory blocks 30-32. This threshold is implemented using the second additional counter 18, the third additional de-distributor 23, and the donor of the south element OR 20. If the second additional counter 18, during the analysis of one of the command repeats (any), counts the number of mismatches I, satisfying the i / i I inequality, signal

from the output of the third additional rarator 23 through the additional element OR 20 sets the first RS flip-flop 21 to the state in which the first additional element AND 26 triggers the majority processing of the information part of the control command. This prevents the false reception of the transformed control command.

Claims (1)

Invention Formula A device for receiving triple-repeatable control commands, containing sequentially connected block of input elements, a majority block, a key block, a shift register and a decoder, sequentially connected AND elements, the first OR element, the first and second pulse counters, and analyzer code feature, pulse distributor, the third pulse counter, the block of OR elements and the second element OR, the first input of which is connected to the first input of the majority block, the combined second inputs and the union The third inputs of the majority block and the second element OR are connected respectively to the second and third outputs of the input information block whose address inputs are connected to the corresponding outputs of the bits of the first pulse counter, the inputs of the selection of the memory cell of the block of memory elements of the input information are connected to the corresponding the outputs of the block of elements OR, the first inputs of which are connected to the corresponding outputs of the bits of the second counter-pulse, the first input and output of the AND element are connected respectively GOVERNMENTAL distributor to the first output pulse and the counting pulse input of the third counter, the second input of the first element. OR is connected to the installation input of the pulse distributor and the clock input of the block of memory elements of the input information, information and clock inputs and the output of the code feature analyzer 0 five 0 five 0 five 0 five 0 five connected respectively to the output of the key block, the clock input of the shift register and the enable input of the decoder, and the output of the second element OR is connected to the second information input of the key block, the information and clock inputs of the block of memory elements of the input information, the second input of the AND element and the outputs of the decoder are respectively, information and clock inputs, input of pulse processing and device outputs, and the block of memory elements of the input information contains the first one; second and third memory blocks, address inputs, memory cell selection inputs, combined information inputs, the combined clock inputs and outputs of which are respectively the address inputs, memory cell selection inputs, information and clock inputs and the first, second and third block outputs elements of the input information, the key block contains the first and second keys, the information and control inputs of which are respectively the first and second information inputs and the first and second control inputs of the block to The keys, the outputs of the first and second keys, combined via the unbundling element, are the output of the key block, the OR block contains the first, second and third OR elements, the first inputs and the combined second inputs and outputs of which are (; respectively the first inputs, the second the input and output of an OR block, characterized in that, in order to increase the noise immunity of receiving control commands, serially connected reference combination memory block, comparator block, first additional pulse counter are introduced s, the first additional decoder, an additional element OR; the first RS trigger and the first additional element AND, whose output connected to the first control input of the key block and the second input of the block of OR elements, are connected in series the second additional decoder, the second RS trigger, the second additional pulse counter, the third RS trigger and the second additional And element, the output of which is connected to the second control input of the key block, serially connected element NOT and additional key, information input and output of which are connected respectively to the output And the element and the clock input of the shift register, and the third supplementary decoder, the outputs of the third pulse counter bits are connected to respective inputs of the second additional block decoder and the memory reference combination. The R input of the third RS flip-flop and the pulse input of the pulse distributor are connected to the corresponding output of the second additional decoder, the second and third outputs of the pulse distributor are connected respectively to the second inputs of the first and second additional elements I, the third inputs of which are connected to the output of the HE element, the input which is combined with the zero input of the first additional counter and, is connected to the direct output of the second RS flip-flop, and the input is set- (SI from | the first additional counter combined with the R input of the first RS trigger and connected to the setup input of the pulse distributor, the output and inputs of the third additional descrambler are connected respectively to the second input of the additional element OR and the corresponding outputs of the bits of the second additional counter, the counting input of which is connected to the output of the comparator, the input which is connected to the output of the second element OR. 1/77 I 8 J Lr-Lr-T Well I 11 FIG. 2 Jl