SU1679644A1 - Digital data receive-transmit system - Google Patents

Description

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of receiving information. The system contains on the transmitting side: sensors 1, gates 2, 6 and 13, register 3 shift, el-OR 4.9 and 11, el-AND 5.10 and 12, switch 7 and counter 8, and on the receiving side: parallel register 14, the decoder address 15, Mr. 16 clock pulses, el-you And 17, 23,

The invention relates to telecommunications and can be used in logical and program control systems.

The purpose of the invention is to increase the reliability of receiving information.

The drawing shows a structural electrical circuit of the proposed system.

The system for transmitting and receiving discrete information contains on the transmitter side sensors 1, first valves 2. shift register 3, first element OR 4, first element AND 5, second valve 6, switch 7, counter 8, second element OR 9, second element AND 10, the third element OR 11, the third element I 12 and the third valves 13, and on the receiving side - parallel pe 27,28 and 29, triggers 18,21,22 and 24, counters

19 and 25 microcycles and addresses, decoder

20 microcycle, el-OR 26, digital indicator 30, sensor 31 and el-comparison of 32 codes. With the successive appearance of pulses at the output of the And 17, the counter .19 increases the state of its code at the output, which is converted by the decoder 20 into a shift of the level of "logical unit" from the first to the last of its output. This is a microcycle polling the status of the bits of the register 3 and sensor 1. Their logical state in the sequential code goes to the receiving side. At the same time, on the receiving side, in each micro-cycle of receiving information, the presence of an accompanying (hardware) pulse is monitored, by which the performance of the system and the reliability of the received information are evaluated, 1 Il.

gistr 14, address decoder 15, clock generator 16, first element 17, first trigger 18, microcycle counter 19, microcycle decoder 20, second 21 and third 22 triggers, second element 23, trigger 24, address 25, element OR 26, third 27, fourth 28 and fifth 29 elements AND, digital indicator 30, sensor 31 and element 32 of the code comparison.

The system works as follows.

At the time of supplying voltage to the system from the power source (not shown), all bits of registers 3 and 14 and counters 8, 19, 25 are set to "0", and the level of the logical unit is set at the direct output of the start trigger 24 and the first output of the decoder 20 . Under the influence of this, 511 ,,,, 1679644A1

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The first level on the direct outputs of the trigger 18, 21 and 22 is set to "zero". As a result, the first input of the element And 17 appears the level of the logical unit, allowing the passage of the pulses of the generator 16 through the element And 17.

When pulses appear at the output of the element And 17, the counter 19 increases the state of its code at the output, which is converted by the decoder 20 into a shift of the level of the logical unit from the first to the last of its output.

When the first pulse arrives at the input of the counter 19, a second pulse appears at the second output of the decoder 20 with the level of a logical unit that is transmitted through the communication wire OR 26 to the input of the counter 8 and the second input of the element 12. When the output pulse appears at the direct output of the first discharge of the counter 8, the level of the logical unit appears, which goes to the first direct output of the AND 10 element and to the first input of the AND 12 element, allowing the pulse to pass to the second clock input of the register 3. By this time, the first input (record) regis 3 pa already present logic-one level for the incoming wire from the output of flip-flop 24 is started. As a result, the level of the logical unit is recorded in the first digit of the register 3, which goes to the second input of the first valve 2 and through the switch 7 to the first input of the second valve 6. By this time, the second inputs of the valves 6 already have the level of the logical unit coming from the output counter 8. Thus, with the first system clock at the output of the second valve 6, the level of the logical unit appears, which through the element OR 9 enters the second unit input of the element AND 10, and at the first unit input the element a AND 10 by this time there is also a logical unit level from the counter output 8. When the pulse at the second output of the decoder 20 ends, the logical zero level appears at the inverse input of the AND 10 element, allowing the accompanying (instrumental) pulse to pass through the And 10 element, then element OR 11 on the combined inputs of the elements And 28 and 29.

When the second pulse arrives at the input of the counter 19, a pulse appears at the fourth output of the decoder 20, which passes through the element 28 at the input of the trigger 21 and sets the level of logic zero at its inverse output. At the same time, under the influence of this pulse, at the unit output of trigger 24, a logical zero level is set, which is fed to the second input of the AND 23 element and to the input of the register 3, blocking the reset of the counter 25 and the level of the logical one to the first register bit 3.

When the third pulse arrives at the input of the counter 19, a pulse appears at the third output of the decoder 20, which arrives at the first input of the element And 27, By this time, the logical zero level is present at the second input of the element And 27 and the trigger 18 remains in the initial state. If by this time the trigger 21 has remained in the initial state due to a failure in the system, then the pulse from the fourth output of the decoder 20 through the element AND 27 enters the input of the trigger 18 and sets the level of the logical unit at its single output, which goes to the digital indicator 30 and includes it. At the same time at the first input of the element And 17 appears the logical zero level from the inverse output of the trigger 18, blocking the passage of pulses to the input of the counter 19. In addition, the pulse from the third output of the decoder 20 enters through the element OR 26 to the input of the counter 8, setting at its first unit output discharge level of logical zero, and at the unit output of the second discharge - the level of logical units. The specified state of the digits of the counter 8 prepares the passage of information through the valves 6 and the element And 5.

When the fourth pulse arrives at the input of the counter 19, a pulse appears at the fifth output of the decoder 20, which arrives at the first input of element And 29. If at this time "first sensor 1 is in the" one "state, then this information Through valve 2, element OR 4 , element AND 5, element IL AND 9 enters the input of element AND 29 and is written to trigger 22. If the first sensor was in the zero state, then the trigger 22 remains in the zero state. The logic level from the single output of the trigger 22 enters all information inputs of the register 14.

When the fifth pulse arrives at the input of the counter 19, a pulse appears at the eighth output of the decoder 20, which is fed to the control input of the decoder 15. As a result, the pulse arrives from the first output of the decoder 15 to the first input (synchronization of the first digit) of the register 14, the output of the first register 14 is set to '' 1 ". If at this time at the second (informational) inputs of register 14 there is a logic level5

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zero, the output of this bit of register 14 is set to “O”.

When the sixth pulse arrives at the input of the counter 19, a pulse appears at the sixth output of the decoder 20, which arrives at the (counting) first input of the counter 25, which increases the state of its output code by one, preparing the address for recording information into the corresponding register bit 14.

When the seventh pulse arrives at the input of the counter 19, a pulse appears at the seventh output of the decoder 20, which sets the counter 19 to "0". After this, the microcycle poll is repeated.

During receipt of the clock pulses at the input of the counter 8 in the first two clock cycles, the logical state of the odd-numbered register 3 and the odd-num sensor 1 is polled, and in the second two clocks of the even-numbered register 3 and the even-num sensor 1.

Thus, with further generation of clock pulses, the level of the logical unit shifts from the low-order bit of the register 3 to the high-order one, which arrives at the inputs of gates 2, b.i and 13 / polls the state of the bits of the register 3 and the-sensor 1. Their logical state is in series code arrives at the receiving side. At the same time, on the receiving side, in each micro-cycle of receiving information, the presence of an accompanying (hardware) pulse is monitored, by which the performance of the system and the reliability of the received information are evaluated. With the help of the address counter 25 and the address decoder 15, discrete information about the status of sensors 1 is addressed and written into the corresponding bits of register 14. Repeating the receive micro cycles continues until counter code 25 does not match sensor code 31. If the codes at the element output coincide 32 code comparison, an impulse appears, under the influence of which the trigger 24 is set to "1". After the end of the current microcycle of reception, the impulse through the first output of the decoder 20 enters through the AND 23 element at the input zero of counter 25 and sets it to “0.” At the same time, the cycle of polling the status of sensors 1 is repeated.

Using switch 7 in each channel of the transmitting side, so many valves 6 and 13 are connected to the digits of register 3. which is equal to the number of sensors 1 connected to valves 2. The last discharge of register 3 also registers

connects to the wire connection. This eliminates the time delay in the channels of information transmission. On the receiving side, the sensor 31 of the code sets a number equal to the total number of sensors 1 connected to all channels of the transmitting side.

Claims (1)

A system for transmitting and receiving discrete information, comprising sensors on each side of the transmitting side, the outputs of which are connected to the first inputs of the corresponding first valves, the outputs of which are connected to the inputs of the first OR element, the output of which is connected to the first single input of the first And element, whose output connected to the first input of the second element OR, the shift register, the outputs of which are connected to the second inputs of the corresponding first valves, while the second input of the second element OR is The information input of the transmitting side, the information output of which is the output of the second element OR, the address input of the transmitting side is the first input of the shift register, and on the receiving side the clock generator, the address counter, the output of which is connected to the first input of the address decoder, the outputs of which are connected to the first inputs parallel register, and the trigger trigger, the output of which is the address output of the receiving side, the information outputs of which are the outputs of the parallel register, which distinguishes by the fact that, in order to increase the reliability of receiving information, the second and third gates, the third element OR, the second and third elements AND, the switch and the counter, the first unit output of which is connected to the first unit input of the second element And with the first input of the third element And, the second input of which is connected to the input of the counter, to the inverse input of the first element And to the inverse input of the second element And, the second single input of which is connected to the output of the third element OR, the inputs of which The second is connected to the outputs of the respective second and third valves, the first inputs of which are connected to the corresponding outputs of the switch, the inputs of which are connected to the corresponding outputs of the shift register, the second input of which is connected to the output of the third And element, the second single input of the first And element is connected to the first inverse output of the counter , the second infers output of which is connected to the second inputs 7 1679644 eight the second inputs of the third valve are connected to the second single output of the counter, the output of the second element AND is connected to the third input of the second element OR, while the counter input is the clock input of the transmitting side, and on the receiving side five elements AND, microcycle counter, microcycle decoder are entered ,, OR element, three triggers, digital indicator, code comparison element and sensor, the output of which is connected to the first input of code comparison element, the second input of which is connected to the output of the address counter and to the first input One digital indicator, the second input of which is connected to the unit output of the first trigger, the inverse output of which is connected to the first input of the first element I, the output of which is connected to the first input of the micro-cycle counter, the output of which is connected to the input of the micro-cycle decoder, the first output of which is connected to the first inputs of the first , the second and third triggers and with the first input of the second element I, the second input of which is connected to the output of the trigger; a start trigger, the first input of which is connected to the output of the code comparison element, the second input of the microcycle decoder is connected to the first input of the OR element, The second input is connected to the third output of the microcycle decoder and to the first input of the third element And, the second input of which is connected to the output of the second trigger, the second input of which is connected to the output of the fourth element And, the first input of which is connected to the second input of the trigger and the fourth output of the decoder microcycle, the fifth output of which is connected to the first input of the fifth element And, the output of which is connected to the second input of the third trigger, the output of which is connected to the second inputs of the parallel register, the output of the generator Ator clock connected to the second input of the first AND gate, the output of the second AND element is connected to the first input of the address counter, the second input of which is connected to the stoma exit she- ₄ decoder microcycle, a seventh output is connected to the second input of counter microcycle, the third element is connected to output of AND with the second input of the first trigger, the eighth output of the microcycle decoder is connected to the second input of the address decoder, and the output of the OR element is the clock output of the receiving side, the information input of which is are combined the second inputs of the fourth and fifth elements I.